RISC-V: Powering the Era of Intelligent General Computing

Charlie Su, President and CTO of Andes Technology, delivered a compelling keynote at the 2025 RISC-V Summit North America, asserting that RISC-V is primed to drive the burgeoning field of Intelligent General Computing. This emerging paradigm integrates AI and machine learning into everyday computing devices, from AI-enabled PCs and smartphones to edge servers, software-defined vehicles, and robotic platforms. Su emphasized that advancements in AI/ML are infusing intelligence into general-purpose computing, enabling applications in personal use, factory automation, surveillance, drones, and autonomous driving (ADAS Levels 0-4). He predicted that robots, as app-enabled platforms, could surpass the smartphone market in scale. To support this, Intelligent General Computing demands a robust ecosystem for both general-purpose tasks and large-scale AI/ML, encompassing software and hardware.

Charlie highlighted RISC-V‘s role in fostering innovations for large-scale AI/ML. A prime example is Meta’s Training and Inference Accelerator (MTIA), which leverages Andes’ vector and scalar cores alongside the Automated Custom Extension (ACE) framework, as detailed in ISCA 2023. Two generations of MTIA have been deployed in Meta’s data centers since 2023, based on RISC-V processors with automated extensions. Other accelerators using SRAM-based Compute-In-Memory include solutions for servers (e.g., RiVos AI SoC), cloud services (SAPEON), photonics-based AI, and ADAS systems. These are powered by Andes cores like AX46MPV, AX45MPV, NX27V, and AX65, demonstrating RISC-V’s versatility in high-performance AI.

The RISC-V software ecosystem is maturing rapidly, bolstered by initiatives like RISE (RISC-V Software Ecosystem), which accelerates open-source software development, improves quality, and aligns efforts for cloud and IoT devices. Java 22/21 support is already in place, with tools spanning compilers (LLVM, GCC, GLIBC), system libraries (FFmpeg, OpenBLAS), kernel/virtualization (Linux, Android, Performance Profiles), and more. Premier members include Andes, Google, Intel, NVIDIA, Qualcomm, and Samsung. Debian’s open-source support underscores this maturity, with RISC-V achieving a 98.4% successful build rate across over 64,000 packages—ranking third overall. Metanoia’s 5G O-RAN software architecture further exemplifies modular, full open-source releases for semi-turnkey solutions.

Andes’ processor lineup is tailored for this era. The AX46MPV offers powerful compute and efficient control, compliant with RVA22+ including AIA and SV38/48/57 virtualization. It features dual-issue for vector/scalar instructions, a Vector Processing Unit (VPU) with VLEN/DLEN from 128-1024 bits, supporting int4-int64 and bf16/fp16-64 formats, plus enhanced ReductionSum. Multicore support reaches 16 cores, with boosted memory via dual-issue load/store, strong outstanding capabilities, and a High-speed Vector Memory (HVM) interface handling multiple OOO requests. Performance gains over AX45MPV include ~18% in SpecInt2006 (5.65 score), over 2x in key vector libraries (libvec, libnn), and +40% bandwidth.

The AX66, a mid-range application processor, is RVA23 compliant with dual vector pipes (VLEN=128), 4-wide frontend decode, 128-entry ROB, 8 execution pipelines, and TAGE-L branch predictor. It supports up to 8 cores, 32MB shared L3 cache (mostly exclusive), and 128/256-bit AXI4 interfaces with IOMMU, APLIC, and CHI. Vector performance yields >10x in libnn key functions (9.6x average), >4x in libvec (3.55x average), and significant crypto boosts (4.7x SHA-256, 10.5x AES-128, 6.4x SM4). Bandwidth increases by 25%.

For high-end needs, the Cuzco series scales to 20 SpecInt2k6/GHz, with patented time-based scheduling via Time Resource Matrix for efficient instruction issuing and power reduction. RVA23 compliant, it features 8-wide decode, 256 ROB entries, 8 pipelines (2 per slice), advanced branch prediction, private L1/L2 caches, up to 256MB shared L3, multiprocessor up to 8 cores, and CHI/256-bit MMIO. Early 5nm implementation targets 2.5GHz, with current SpecInt2006 at ~18/GHz, using 7M gates for CPU and 4.5M for 2MB L2.

Andes enhances the ecosystem with AndesAIRE, an “AI Runs Everywhere” end-to-end solution, including IDEs, NN SDKs, compilers (MLIR, TVM), interpreters (ONNX Runtime, PyTorch), and accelerators like AndLA 1350. OS support is comprehensive: RISC-V specs (RVA22/23 profiles, SoC platforms), Linux distros (Debian, Fedora, Ubuntu, verified by Andes), upstream kernel features (strace/ftrace, Perf, HIGHMEM, CPU hotplug, ongoing Suspend-to-RAM and PowerBrake), bootloaders (U-Boot, OpenSBI), and RTOS (FreeRTOS, Zephyr, Thread-X).

Bottom line: Charlie noted Andes leads RISC-V IP shipments with rich portfolios. The latest processors—AX46MPV for compute/control, AX66 to Cuzco for performance—position Andes strongly. The RISC-V ecosystem is ready for Intelligent General Computing, promising transformative impacts across industries.

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