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Andes Technology Hosts First-Ever RISC-V CON in Munich, Powering Next-Gen AI and Automotive Solutions

AmandaK

Administrator
Staff member
Munich, Germany – October 9, 2025 – The future of AI and automotive computing is here — and it’s powered by RISC-V. As industries race toward smarter, safer, and more efficient systems, engineers are embracing the open and extensible RISC-V architecture to design the next generation of intelligent SoCs.

Now, for the first time, Andes Technology is bringing its flagship event – Andes RISC-V CON – to Munich, Germany! Join us on October 14, 2025, for half day of innovation, insight, and connection at the heart of Europe’s automotive and technology hub.

At Andes RISC-V CON Munich, you’ll experience:
  • - Inspiring keynotes from global RISC-V leaders and technology pioneers
  • - Real-world success stories from cutting-edge AI and automotive applications
  • - Hands-on demos of Andes’ latest RISC-V QiLai platforms running Android
  • - Exclusive networking with engineers, researchers, and ecosystem partners driving the RISC-V revolution
What to Expect:Hear directly from RISC-V innovators as they explore the latest trends, technologies, and success stories.

- Frankwell Lin, Chairman & CEO, Andes Technology

His talk highlights RISC-V’s growing adoption across AI, automotive, 5G, and more, showcasing Andes’ innovations, customer success stories, and a comprehensive software environment for optimized, application-specific solutions.

- Dr. Charlie Su, President and CTO of Andes Technology
His talk provides the background of how AI/ML is rapidly transforming the general-purpose computing landscape, shows that RISC-V ecosystem is ready to take on the emerging requirements, and explores Andes latest high-performance and vector processors, designed for the Intelligence General Computing.

- Michael Platzer, Computer Architect, Axelera AI
Michael will present Axelera AI’s RISC-V–based in-memory computing platform, showcasing its custom vector processor, ecosystem contributions, and innovations that make AI acceleration more efficient and accessible.

- Niraj Dengale, Senior FAE, Andes Technology
In a deep dive into security, Niraj will showcase Andes AndeSentry™ — a comprehensive security framework that builds a trusted, standards-based foundation for protecting RISC-V embedded systems from boot to runtime.

- Tommaso Serafin, Sales Manager EMEA, Andes Technology
Tommaso will focus onhow advanced automotive CPUs enhance safety, efficiency, and user experience while driving the evolution of intelligent, connected, and autonomous vehicles.

- Markus Goehrle, Specialist Embedded Systems Engineer, Lauterbach
Markus will demonstrate howLauterbach’s tools leverage RISC-V debug and trace interfaces to streamline development. Real-world use cases with Andes A25/A27 cores will highlight simplified debugging in complex multicore environments.

Why RISC-V Matters

According to The SHD Group’s April 2025 report, Andes Technology is the global leader in RISC-V IP market share. The growing complexity of AI and automotive applications has pushed traditional processor architectures to their limits. RISC-V’s modular and extensible design empowers developers to overcome these challenges with unmatched efficiency, scalability, and design freedom.

The momentum is undeniable — SHD Group projects that by 2030, more than 16.2 billion SoCs will ship annually based on RISC-V, with total market revenue expected to reach $92 billion USD.

Don’t Miss Out

Be part of the RISC-V movement. Be part of the future.

Join Andes RISC-V CON Munich 2025 and discover how open computing is transforming AI, automotive, and beyond.

Event Date/Time: October 14, 2025 | 1:00 PM – 6:00 PM

Location: Barcelona Hall, Smartvillage Bogenhausen, Munich, Germany

Register now!

About Andes Technology


As a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is driving the global adoption of RISC-V. Andes’ extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters. With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, consumer electronics, data centers, and mobile devices. Over 17 billion Andes-powered SoCs are driving innovations globally. Discover more at www.andestech.com and connect with Andes on LinkedIn, X (formerly Twitter) , YouTube and Bilibili.

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