Analog Bits at the 2025 Design Automation Conference

Analog Bits attends a lot of events. I know because I see them a lot in my travels. Lately, the company has been stealing the show with cutting-edge analog IP on a broad range of popular nodes and a strategy that will change the way design is done. Analog Bits is quietly rolling out a new approach to system design. One that delivers a holistic approach to power management during the architectural phase of design The company believes this is the only way to achieve the required power and performance for demanding next-generation AI systems.

In their words, “Analog Bit is the leading energy management IP company, making power safe, reliable, observable and efficient.” There is a lot to unpack in that statement, and a lot to see at the Analog Bits booth #1320 at DAC. Let’s look at the IPs Analog Bits has available across several foundries. There are many more in the works.

TSMC 2nm

Analog Bits recently completed a successful second test chip tapeout at 2nm, but the real news is the company will be at DAC with multiple working analog IPs at 2nm. A wide range PLL, PVT sensor, droop detector, an 18-40MHz crystal oscillator, and differential transmit (TX) and receive (RX) IP blocks will all be on display.

TSMC 3nm

Four power management IPs from TSMC’s CLN3P process will also be demonstrated. These include a scalable low-dropout (LDO) regulator, a spread spectrum clock generation PLL supporting PCIe Gen4 and Gen5, a high-accuracy thermometer IP using Analog Bits patented pinless technology, and a droop detector for 3nm.

Other TSMC Nodes, 4nm to 0.18u

Analog Bits has been an OIP partner with TSMC since 2004 and has a large portfolio of clocking, sensors, SERDES and IO IP’s. You can check out the availability at the company’s product selector website at https://www.analogbits.com/product-selector/.

GlobalFoundries 12LP, 12LP+, 22FDX

An integer PLL, FracN/SSCG PLL, PCI G3 ref clock PLL, PVT sensor, and power on reset are all available in both GF 12LP and 12LP+. A PCI G4/5 ref clock PLL is available on GF 12LP+. A broad array of automotive IP is also available in GF 22FDX including voltage regulators, power on reset, PCT sensors and IO’s.

Samsung 4LPP, 8LPU and 14LPP

An integer PLL, PVT Sensor, power on reset, and droop detector are available on Samsung 4LPP. An automotive grade PLL, PVT sensor, and PCIe Gen4/5 SERDES are available on Samsung 8LPP/8LPU. An integer PLL, PVT sensor, and PCI Gen4 SERDES are available on Samsung 14LPP.

About the Intelligent Power Architecture

Optimizing performance and power in an on-chip environment that is constantly changing with on-chip variation and power-induced glitches can be a real headache. Multi-die design compounds the problem across many chiplets.

The Analog Bits view is that this problem cannot be solved as an afterthought. Plugging in optimized IP or modifying software late in the design process won’t work. The company believes that developing a holistic approach to power management during the architectural phase of the project is the answer.

So, Analog Bits is rolling out its Intelligent Power Architecture initiative. There is a lot of IP and know-how that work together to make this a reality. If power optimization is a challenge, you should stop by booth #1320 at DAC and see what solutions are available from Analog Bits.

To Learn More

You can find extensive coverage of Analog Bits on SemWiki here.  You can also visit the company’s website to dig deeper. See you at DAC.

Also Read:

Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy

2025 Outlook with Mahesh Tirupattur of Analog Bits

Analog Bits Builds a Road to the Future at TSMC OIP