RRAM Redux

Advanced memory technologies are a perennially hot topic thanks to a proliferation of data-hungry applications pushing our demand for more capacity and performance at less power and area. Among several technology contenders is Resistive RAM or RRAM (also called ReRAM). In this technology a conducting filament is grown through a dielectric on application of a voltage. RRAM is promoted as a replacement for traditional flash (non-volatile) memories and in principle should be a significantly superior solution. It is lower energy, bit-writeable and much faster to read and write. It also lends itself to 3D stacking which could enable high capacities as well as RRAM stacked directly on top of logic.

But RRAM has offered this hope before, only to get bogged down in an inability to deliver high memory capacity. Building small (~Kb) memories demonstrated all the expected advantages of RRAM – reads and writes in microseconds or less compared with milliseconds for flash, and lower voltage operation with much more fine-grained writeability, thus lower power. But capacity was limited by sneak-path currents on read. In RRAM writing a cell is voltage-based, but reading is current-based; when current flows through a cell you want to read, it also flows through neighboring cells, which makes it difficult to confidently interpret the read value. Those added currents also negate the power advantage.

Crossbar positions themselves as the leader in this field, claim they have solved the sneak path problem and have transitioned their technology to production. They were founded in 2010 and came out of stealth mode in 2013; they have raised over $80M so far, including a $35M D-round last year (per CrunchBase), so they certainly have the credibility and funding to play in this game. I talked with Sylvain Dubois (VP of marketing and biz dev) at ARM TechCon last month to get a sense of why they believe they have a scalable solution.

Sylvain first agreed that the big foundries have rejected most RRAM implementations so far because they don’t scale in size. However, Crossbar announced at IEDM in 2014 their own solution to the sneak path problem, using a method they call field-assisted superlinear threshold (FAST) selection which provides very high selectivity. They reported the method suppresses sneak currents in a 4Mb array to below 0.1nA across the commercial temperature range and selectors reliably cycle over 10[SUP]11[/SUP] cycles. He also noted that RRAM has a lower leakage current than flash as feature size decreases. Crossbar summarize a partial comparison of their RRAM with flash technologies below.

An important feature of the Crossbar RRAM is that it is compatible with standard CMOS processes, which makes it usable as an embedded macro in a larger design. They announced earlier this year a partnership with SMIC to provide this technology on a 40nm process. They have built an 8Mbit reference macro which is now available for licensing and they are actively working with customers to adapt the macro to their needs. They expect to pursue opportunities in embedded and IoT applications especially (obviously) in China. They are also working on a partnership with one of the mainstream foundries at a more advanced process node, announcement still TBD.

Based on density measurements they have gathered so far, Crossbar expects they should be able to scale up to terabits per die. If they are right, this could be a real game-changer for non-volatile memory both in embedded and mass storage applications. You can get an overview of Crossbar technology and applications starting HERE. There’s a detailed set of slides on 3D capabilities HERE.

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