Andes Technology is Expanding RISC-V’s Horizons in High-Performance Computing Applications

By: Dr. Charlie Su, President and CTO, Andes Technology Corp.

At Andes Technology, we are excited to share some of our latest advancements and insights into the growing role of RISC-V in several high-performance applications. According to the SHD Group report, “IP Market RISC-V Market Report: Application Forecasts in a Heterogeneous World,” our processor IPs account for 30% of RISC-V shipments, making Andes the number one competitor in the market. This gives us unique visibility into the deployment of the RISC-V ISA worldwide. Our customers offer products for a diverse range of applications across AI/ML, automotive, communication/networking, microcontroller, mobile, and storage sectors.

Leading Innovations in AI Acceleration

AI has been one of our largest licensing markets for our vector processors and advanced CPUs, targeting applications ranging from low-power edge devices—such as smart home devices, wearable health monitors, predictive maintenance in industrial settings, and autonomous drones and robots—to the high-performance cloud AI and data centers, with customers like Meta and Sapeon.

Meta announced their first Meta Training Inference Accelerator (MTIA) at ISCA 2023. It featured an 8×8 64 PE (processing element) array. Each PE includes a processor subsystem incorporating two configurations of the Andes AX25-V100, the predecessor of Andes popular NX27V vector processor. Meta also leveraged Andes Custom Extensions (ACE) and COPILOT tools to heavily customize the cores to their unique requirements, significantly reducing their design teams’ engineering time.

Meta noted in their ISCA presentation: “Each PE contains two RISC-V cores… and are heavily customized to suit the functionalities needed… The set of customizations includes custom interfaces, custom registers, custom instructions, and custom exceptions… The focus and strategy when architecting the accelerator therefore has been on adopting and reusing suitable pieces of technology, as well as tools and environments, from vendors and the open-source community….”

Our NX27V and AX45MPV vector processors, and other advanced Andes cores, are key components in next-generation in-memory computing solutions. Customers such as Axelera, Houmo.AI, Rain AI, and TetraMem leverage our technology for their in-memory computing AI accelerators. Most recently, our customer Rivos commented that our NX45 in their high-end AI SoC is the only RISC-V core passing their rigorous verification tests.

A pioneer in compute-in-memory (CIM) technology, Rain AI licensed Andes’ AX45MPV RISC-V vector processor. The AX45MPV CPU future-proofs Rain’s CIM-based NPU by allowing the addition of custom instructions to encapsulate the CIM computing blocks, thereby greatly simplifying software development efforts, esp. for the AI compiler. Andes Custom Extension framework and its automated COPILOT tool streamlines this customization process as highlighted in the Rain AI’s talk in the recent Andes RISC-V CON.

AI continues to be an area of rapid innovation, making it a perfect fit for RISC-V.  For example, Lightelligence is developing photonics-based AI accelerators performing high-speed matrix multiplication—another exciting area where our vector processors play a crucial role.

Automotive and ADAS (Advanced Driver Assistance Systems) are also growth markets.  Our automotive customers use our Vector and Safety-Enabled family of RISC-V cores across a variety of applications including in-cabin monitoring, display, radar, and sensing/control.  Multiple customers have utilized our fully ISO26262-compliant products and safety packages, achieving product safety certification in record time!

Additionally, our traditional markets such as processors for media-rich computing platforms (e.g, smartphones, tablets, and TVs), signal processing in wireless communications, and general-purpose control, remain strong.  For example, Renesas uses Andes AX45MP for their Linux-capable MPU, the RZ/Five.  The significant growth in high-performance AI and Automotive combined with the rapidly expanding software ecosystem is also driving growth in the high-performance general-purpose processing segment.

New and repeat customers continue to value the flexibility, openness, and rapid time-to-market that is enabled by Andes commercial RISC-V IP coupled with our COPILOT toolset for custom extensions.  We are seeing this growth persist in our traditional markets of embedded control, DSP, and real-time systems.  More importantly, this growth is accelerating in AI, Automotive, and General Compute.

Enhanced Software Ecosystem and Innovations

The RISC-V software ecosystem for control processors is rapidly expanding, with support from GNU, LLVM, Linux, and Google’s official support for Android. Linux already has robust RISC-V support, from the toolchain to booting into various Linux distributions. The RISC-V Software Ecosystem (RISE) Project, formed by Andes and other key RISC-V companies, is actively working to enhance open-source support for application processors, recently bringing up support for Java 21 and 22.

Andes is heavily involved in RISE, currently contributing to compilers for supporting ever-increasing memory space and to QEMU (Quick EMUlator) for adding new RISC-V extensions such as IOPMP, which is a powerful fast simulation framework to enable early software exploration and development while SoC architecture is still on the drawing board.

Under the RISE project, Andes is also responsible to portimize (port & optimize) the entire OP-TEE (Open Portable Trusted Execution Environment), a trusted application framework, to RISC-V. With OP-TEE, RISC-V will have a competitive offering to ARM’s TrustZone software. OP-TEE provides the software level protection, while ePMP (Enhanced Physical Memory Protection) and IOPMP (Input/Output Physical Memory Protection) hardware level protection. These advanced memory protection features enhance system security and reliability by providing fine-grained control over permissions of memory accesses from RISC-V processors and other DMA-capable controllers, crucial for high-security applications. The porting of OP-TEE calls for significant work in TEE Client API and OP-TEE Linux Driver in the Non-secure World as well as TEE core API and OP-TEE OS in the Secure World. Underlying the Secure and Non-secure World is the OpenSBI layer, which Andes will enhance with OP-TEE extensions. OpenSBI (Open Supervisor Binary Interface) is another critical component in the RISC-V ecosystem, providing the necessary firmware layer to boot and manage RISC-V operating systems and hypervisors.

Regarding Android, Google has specified the base requirements for RISC-V in the Compatibility Definition Document (CDD). This includes RVA22 plus vector, vector crypto, and hypervisor support. Andes has been working on the ongoing Android Open-Source Project (AOSP) software by bringing them to run on QEMU and porting it to our non-compatible hardware to achieve faster performance for Android. During this process, we even identified some generic bugs present in ARM builds, which Google acknowledged and fixed.

We also focused on optimizing computational libraries using RISC-V Vector extension (RVV), such as libjpeg—the widely used library for handling JPEG images, offering efficient compression, decompression, and manipulation capabilities, and working on optimization for ART (Android Runtime). The Android Runtime (ART) represents a significant evolution in the Android platform’s runtime environment, offering substantial improvements in performance, efficiency, and developer productivity over its predecessor, Dalvik. By leveraging AOT (Ahead-of-Time) and JIT (Just-In-Time) compilation, enhanced garbage collection, and better debugging tools, ART provides a more responsive and efficient runtime for Android applications.

Conclusion

Andes Technology continues to deliver advanced RISC-V processor IP while making extensive contributions to its software ecosystem. Our collaborations with industry leaders in the AI, automotive, and computing sectors highlight the versatility and potential of RISC-V architecture. Through our robust hardware solutions and the ever-enriched RISC-V software ecosystem, we are paving the way for RISC-V to become a mainstream choice for high-performance computing applications. With ongoing efforts in compiler enhancements, runtime and library optimizations, trusted application framework, and support for critical industry standards, Andes Technology is leading the way in realizing the full potential of RISC-V. We are excited about the future possibilities and innovations, solidifying our position in the evolving landscape of high-performance computing.

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