High-speed, low-power, Hybrid ADC at IP-SoC

Andrew Levy and I both worked at Intel and Opmaxx, and I knew that he was now working at Alphacore, an IP company specializing in mixed-signal, RF, imaging and rad-hard applications. I was curious what Alphacore was up to, so at the IP-SoC Silicon Valley 2022 event I watched the ADC presentation from Ken Potts, COO of Alphacore. Mr. Potts has been in the semiconductor industry for over three decades, including stints at Silicon Technologies, Cadence, Virage Logic,  Compass Design Automation and VLSI Technology.

I learned from a video interview at the event that Alphacore doubled in size during 2021, and is on track to double again in 2022, so that says a lot about their success in the IP marketplace. Ken’s presentation at IP-SoC was all about their progress in designing hybrid ADC circuits. Applications for RF data converters include: 5G radios, beamforming, direct to RF sampling, and phased array architectures. The challenge is how to achieve high bandwidth while also consuming low power.

The ideal process technology for delivering low power has been FDSOI, so Alphacore has done data converter designs with both STMicroelectronics 28nm, and Globalfoundries 22nm. FDSOI delivers about 70% lower power when compared to a 28nm bulk CMOS process node, so that’s a compelling reason to design with FDSOI. Another attraction for choosing FDSOI technology is that it has tolerance to ~100krad TID, something that aerospace designers are concerned about for reliable operating in orbit.

Mr. Potts shared that they have designed a 10-bit, 5GS/s ADC, that consumes only 19.7mW at 5GS/s, using a 800mV supply. As you lower the sampling to 3GS/s the power dips even lower to just 12.8mW.

With ADC circuits there’s a question of gain and offset errors, so the good news is that Alphacore has an auto-calibration algorithm to eliminate interleaving spurs as shown below in the output spectrum results:

For ADC circuits there’s a Figure Of Merit (FOM) to help compare performance, and the formula is Power / (Fs * 2^ENOB), and plotting Alphacore results shows about a 10X lower power while achieving GS/s conversion rates:

ADC IP Choices

There are several ADC IP blocks to choose from that use the STMicroelectronics 28nm process:

• 6-bit, 5GS/s at 14mW – A6B5G
• 9-bit, 1GS/s at 2mW – A9B1G
• 10-bit, 2.4GS/s at 6mW – A10B2G
• 4-bit, 20GS/s Flash ADC – A4B20G

ADC circuits with 22FDX from Globalfoundries include several choices:

• 10-bit, 3GS/s at 13mW – A10B3G
• 10-bit, 5GS/s – A10B5G

The complete table of ADC offerings show which IP blocks are verified GDS II, silicon validated, or in foundry qualification status:

Design Kit

When you work with an IP vendor like Alphacore, they deliver to you a complete set of files so that you can place your converter block in a design, and complete your integration with simulation, verification and implementation:

• GDSII layout file
• RTL files
• Schematic
• Abstract view
• All DRC/LVS logs
• Extracted view
• Extracted simulation model
• Verilog-AMS models
• Guide for DFT and I/O requirements

Alphacore Customers

The actual list is proprietary, but just be assured that the customers represent many segments, like: mil-aero, image sensor, advanced electronics, defense contractors, radars, national laboratories, research agencies. The ADC IP products are being used in six end segments:

• Wireless and wireline communications
• Defense applications
• Test equipment
• Imaging and Lidar
• Automotive
• Scientific & Industrial Instrumentation

Summary

I was pleased to learn about the rapid growth at Alphacore, which only validates there strong position in hybrid ADC IP blocks, achieving high-bandwidth at low power by clever design and use of FDSOI process technology. They have design kits in place, and most of their IP is already silicon proven, so that makes it a safe choice.

Related Blogs

• CEO Interview: Dr. Esko Mikkola of Alphacore