Semiwiki on LinkedIn Semiwiki on X.com Semiwiki RSS Feed Register / Log In

FPGA/ASIC/SOC design

  1. Events
  2. FPGA/ASIC/SOC design

Events Search and Views Navigation

Event Views Navigation

Today

WEBINAR: Demystifying Clock Domain Crossings (CDC) and Synchronization Circuits

Online

Demystifying Clock Domain Crossings (CDC) and Synchronization Circuits Webinar Description This one-hour webinar will discuss all of the basics of what clock domain crossings (CDCs) are and how you can navigate them safely. We will discuss how to do single bit CDCs, several methods for CDC busses, and also the Xilinx Parameterized Macros (XPM) for …

Continue reading "WEBINAR: Demystifying Clock Domain Crossings (CDC) and Synchronization Circuits"

Free

WORKSHOP: Versal Adaptive SoCs 101: Quick Start Guide to Integration and Implementation

Online

Versal Adaptive SoCs 101: Quick Start Guide to Integration and Implementation Workshop BLT Engineers have successfully deployed designs to Versal devices for Clients. Learn from the experts. This 4-hour online workshop explores the AMD Versal adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different …

Continue reading "WORKSHOP: Versal Adaptive SoCs 101: Quick Start Guide to Integration and Implementation"

Free

WEBINAR: AMD Versal AI Engine Tool Flow Explained: Enhancing Your Development Journey

Online

REGISTER: https://us02web.zoom.us/webinar/register/5517125835521/WN_ZCmAh5TcRYeo7EWd4sM6vA AMD Versal AI Engine Tool Flow Explained: Enhancing Your Development Journey In this webinar, learn how to get started programming the Versal AI Engines using the Vitis IDE. This session provides a thorough introduction to the Vitis IDE for AIE development, and how to use the AI Engine Simulators to quickly develop and …

Continue reading "WEBINAR: AMD Versal AI Engine Tool Flow Explained: Enhancing Your Development Journey"

Free

Mastering the Porting of Code to RISC-V Architecture

ACL Digital brings to you an exciting webinar series covering all aspects of the RISC-V Ecosystem. Sign up for the exclusive webinar “Porting of Code to RISC-V Architecture,” on May 16, 8.30 a.m. to 9 a.m. PST. While RISC-V presents a simpler alternative to the complex ISAs of the past, its simplicity introduces its own challenges. Gain crucial insights to mitigate challenges and be future-ready.