DVCon 2018 Mentor Graphics and SemiWiki

DVCon turns 30 this year which is a very big deal. My oldest child also turns 30 this year which really puts things in perspective looking back at what we have all accomplished during that time. DVCon originally started as a user’s group at the 1988 Design Automation Conference in Anaheim California and the rest as they say is history.

This year’s DVCon will be a part of SemiWiki history as we release our next ebook “SoC Emulation—Bursting Into Its Prime” in collaboration with Dr. Bernard Murphy and the Mentor Emulation Team. Bernard will be signing copies at DVCon so stop on by the Mentor Booth #1101 and get a signed copy.

Mentor of course is the king of verification so you will see a lot of Mentor at DVCon starting with the Accellera and Verification lunches followed by a plethora of technical sessions, panels, tutorials, and poster sessions. I will be wandering around on Tuesday and Wednesday and it would be a pleasure to meet you, absolutely.

SPONSORED LUNCHEONS
Accellera Lunch Featuring the 2018 Technical Excellence Award and Accellera Standards Activities
Monday, February 26, 12:00pm – 1:30pm | Pine/Cedar
Speakers:

• SystemC – Trevor Wieman, Intel and Frederic Doucet, Qualcomm
• Verilog AMS – Scott Little, Maxim Integrated
• SystemRDL – Steve Russell, Zyzyx
• UVM – Justin Refice, NVidia
• Portable Stimulus – Tom Fitzpatrick, Mentor, a Siemens Business

Validation: Verification’s Big Brother – “I Wanna Go Fast”
Wednesday, February 28, 12:00pm – 1:15pm | Pine/Cedar
Speakers: Stephen Bailey – Mentor, A Siemens Business
Doug Amos – Mentor, A Siemens Business

TECHNICAL SESSIONS
1.1 Clock Domain Crossing Challenges in Latch Based Designs
Tuesday, February 27, 9:00am – 10:30am | Oak
Speaker: Madan M. Das – Mentor, A Siemens Business
Authors: Madan M. Das – Mentor, A Siemens Business
Chris Kwok – Mentor, A Siemens Business
Kurt Takara – Mentor, A Siemens Business

1.2 Using Formal to Exhaustively Determine Unsafe Clock Ratios Between Asynchronous Blocks
Tuesday, February 27, 9:00am – 10:30am | Oak
Speaker: Eric Hendrickson – NASA’s Jet Propulsion Lab & Jet Propulsion Lab
Authors: Eric Hendrickson – NASA’s Jet Propulsion Lab & Jet Propulsion Lab
Bill Au – Mentor, A Siemens Business
Joe Hupcey III – Mentor, A Siemens Business
Richard Ilaca – Mentor, A Siemens Business

2.2 Building Portable Stimulus Into Your IP-XACT Flow
Tuesday, February 27, 9:00am – 10:30am | Fir
Speaker: Matthew Ballance – Mentor, A Siemens Business
Authors: Petri Karppa – Nokia
Lauri Matilainen – Nokia
Matthew Ballance – Mentor, A Siemens Business

5.1 Transparently Checkpointing Software Test Benches to Improve Productivity of SoC Verification in an Emulation Environment
Tuesday, February 27, 3:00pm – 4:30pm | Oak
Speaker: Ankit Garg – Mentor, A Siemens Business
Authors:
Ankit Garg – Mentor, A Siemens Business
Suresh Krishnamurthy – Mentor, A Siemens Business
Gene Cooperman – Northeastern Univ.
Rohan Garg – Northeastern Univ.
Jeff Evans – Mentor, A Siemens Business
Neil Rosenberg – Intel Corp.

5.3 UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer
Tuesday, February 27, 3:00pm – 4:30pm | Oak
Speaker: Ritesh Goel – Mentor, A Siemens Business
Authors:
Marcela Zachariasova – Codasip Ltd.
Lubos Moravec – Codasip Ltd.
John Stickley – Mentor, A Siemens Business
Hans van der Schoot – Mentor, A Siemens Business
Shakeel Jeeawoody – Mentor, A Siemens Business

6.2 Debugging Functional Coverage Models get the Most out of Your Cover Crosses
Tuesday, February 27, 3:00pm – 4:30pm | Fir
Speaker: Mennatallah Amer – Mentor, A Siemens Business
Authors: Mennatallah Amer – Mentor, A Siemens Business, Amr A. Hany – Mentor, A Siemens Business

8.3 UVM and C Tests – Perfect Together
Wednesday, February 28, 10:00am -12:00pm | Oak
Speaker: Rich Edelman – Mentor, A Siemens Business
Author: Rich Edelman – Mentor, A Siemens Business

12.1 Whose Fault Is It Formally? Formal Techniques for Optimizing ISO 26262 Fault Analysis
Wednesday, February 28, 3:00pm – 4:30pm | Fir
Speaker: Ping Yeung – Mentor, A Siemens Business
Authors: Ping Yeung – Mentor, A Siemens Business
Doug Smith – Mentor, A Siemens Business
Abdelouahab Ayari – Mentor, A Siemens Business

13.1 Unveil the Mystery of Code Coverage in Low-Power Designs:Achieving Power Aware Verification Closure
Wednesday, February 28, 3:00pm – 4:30pm | Monterey/Carmel
Speaker: Madhur Bhargava – Mentor Graphics (India) Pvt. Ltd.
Authors: Madhur Bhargava – Mentor Graphics (India) Pvt. Ltd.
Durgesh Prasad – Mentor Graphics (India) Pvt. Ltd.
Pavan Rangudu – Mentor, A Siemens Business

13.2 Low Power Coverage: The Missing Piece of Dynamic Simulation
Wednesday, February 28, 3:00pm – 4:30pm | Monterey/Carmel
Speaker: Progyna Khondkar – Mentor, A Siemens Business
Authors: Progyna Khondkar – Mentor, A Siemens Business
Ping Yeung – Mentor, A Siemens Business
Gabriel Chidolue – Mentor, A Siemens Business

13.3 Low Power Apps: Shaping the Future of Low Power Verification
Wednesday, February 28, 3:00pm – 4:30pm | Monterey/Carmel
Speaker: Awashesh Kumar – Mentor Graphics (India) Pvt. Ltd.
Authors: Awashesh Kumar – Mentor Graphics (India) Pvt. Ltd.
Madhur Bhargava – Mentor Graphics (India) Pvt. Ltd.
Pankaj Gairola – Mentor Graphics (India) Pvt. Ltd.
Vinay K. Singh – Mentor Graphics (India) Pvt. Ltd.

PANELS
The Right Tool (or Tools) for the Toughest Verification Tasks
Wednesday, February 28, 1:30 – 2:30 | Oak/Fir
Moderator: Jean-Marie Brunet

Emulation, simulation, formal verification and FPGA prototyping, along with a mix of methodologies, are often evaluated by verification groups to assess their ability to solve every conceivable verification challenge. Some verification groups tout emulation as the primary verification technology as simulation reaches its outer limits and FPGA prototyping is consigned to smaller designs. They now consider emulation to be among the most capable tools to meet their challenging chip design verification requirement through better reliability, more use models and greater flexibility. Of course, the verification checkerboard benefits from the adoption of formal verification as it too has more use models and a significant number of expert users. Accellera’s Portable Stimulus standard could play some role in the future, predicts a handful of verification engineers. New developments on the verification front promise to fuel a fascinating discussion among panelists who will describe how decisions are made about which tools are implemented in a design verification flow. And how budgets are allocated. As users, they will explain why some tools dominate today’s flow and others not so much.

TUTORIALS
Portable Test and Stimulus: The Next Level of Verification Productivity is Here
Monday, February 26, 9:00am – 12:00pm | Oak/Fir
Speakers: Tom Fitzpatrick (Mentor, A Siemens Business), Faris Khundakjie (Intel Corp.), Sharon Rosenberg (Cadence Design Systems, Inc.), Adnan Hamid (Breker Verification Systems, Inc.), Srivatsa Vasudevan (Synopsys, Inc.), Karthick Gururaj (Vayavya Labs Pvt., Ltd.)

Why reinvent the wheel? Up until now, verification teams had been unable to reuse tests as their efforts progressed from virtual platforms to RTL, block-level to system-level or from simulation to emulation, prototyping or silicon. The advent of UVM, constrained-random verification and functional coverage improved the reusability of portions of the verification environment, but these advances have not been able to enable reuse of verification intent throughout the product development process. Accellera formed the Portable Stimulus Working Group to produce a standard that would allow just this sort of verification intent reuse. This in-depth technical tutorial will focus on a set of typical design use-cases from a variety of applications and show how to use the Portable Test and Stimulus Standard to create an abstract model of your verification intent. The tutorial will then demonstrate how these models can be used to generate scenarios to be executed on the different platforms and environments used in your development process, and how the models can be reused and leveraged from project to project.

For each application, we will show:

• How to model the critical verification intent
• How that model may be used to generate multiple compatible coverage-centered scenarios
• How to map that intent into multiple target-specific implementations
• How the declarative semantics of the model drive the generation of executable tests on different platforms to implement the desired scenarios

IEEE-Compatible UVM Reference Implementation and Verification Components
Monday, February 26, 2:00pm – 5:00pm | Oak/Fir
Speakers: Mark Peryer (Mentor, A Siemens Business), Justin Refice (Nvidia Corp.), Mark Strickland (Cisco Systems, Inc.), Uwe Simm (Cadence Design Systems, Inc.), Srivatsa Vasudevan (Synopsys, Inc.)

On April 11, 2017, the IEEE Standards Association (IEEE-SA) approved the IEEE 1800.2™ Standard for Universal Verification Methodology (UVM). For the tens of thousands of UVM verification engineers, this milestone connects teams to a standard recognized worldwide. However, the milestone does come with change. On one hand, there are many improvements and new features in the IEEE standard. On the other hand, there are changes to the both the standardized and undocumented APIs that many engineers accessed in the Accellera reference implementation to build their verification components.

This tutorial will introduce engineers to the new reference implementation aligned with IEEE 1800.2 created by the Accellera UVM WG. The speakers will use the new reference implementation to describe the new features and changes relative to UVM 1.2. Engineers attending the tutorial will learn the steps they need to take to update their verification components to be IEEE-compatible. Code examples and interactive discussions with members of the Accellera UVM WG will help engineers gain the practical knowledge they need to adopt the IEEE 1800.2™ Standard for UVM.

Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-Chips
Thursday, March 1, 8:30am – 12:00pm | Siskiyou
Speakers: Ellie Burns, Gabriel Chidolue, Guilaume Boillet

Driven by process technology needs, government legislation, and continued product integration and miniaturization, reducing power consumption is a mainstream and essential design requirement for many industry segments; including networking, mobile, automotive, consumer, and IoT. Because of this, many designs now employ sophisticated power management techniques. For example, design teams implement more power domains per design where each power domain can be placed in many different power states. Unfortunately though, most project managers lack a standard metric for power verification, and because of this do not know how well power management is verified Besides using power management techniques, design teams are also trying to reduce their power in the RTL design process by reducing unnecessary switching activity. This process can be difficult and the ultimate effect from RTL modifications are hard to predict. Lastly, to get a comprehensive methodology for both power measurement and power reduction, it is important to have realistic and accurate switching scenarios for particular power modes. Again, these can often be difficult to create and depend on very large datasets to drive verification results. In this tutorial, we will step through a complete low-power methodology, and explore the different types of metrics needed at different phases of the design process. It will cover a new and unique low-power coverage methodology that enables designers to verify and track how well they have tested their power management architecture. It will also show how to track not only metrics for how much power is used in the RTL, but also how much power is still being wasted and has potential to be reduced for IP qualification. Finally, it will step through how to bring real power scenarios testing into both your power measurement and management coverage metrics to provide the final phase of power verification and validation.

How to Stay Out of the News with ISO26262-Compliant Verification
Thursday, March 1, 2:00pm – 5:30pm | Siskiyou
Speakers: Doug Smith, Charles Battikha

As the transportation industry continues to increase the amount of electronics and embedded software included in its products, systems and semiconductor makers must now consider the fault tolerance of their product offerings to customers in this rapidly growing market. Fortunately, the ISO 26262 standard defines the safety level of a design via specific safety goals, safety mechanisms, and fault metrics. However, even though there are sections of ISO 26262 dedicated to electronic systems in general, and semiconductors in specific, the mapping of the specification to the implementation of design and verification best practices is not specifically delineated.

Hence, in this tutorial you will learn:

• What are the basics of the ISO26262 standard as it applies to requirements for electronic design & verification of safety critical products
• How to estimate the safety level of a design by defining safety goals, selecting “safety mechanisms”, and specifying fault metrics
• How today’s dynamic, static, and hardware-assisted verification flows can be employed to verify the safety-critical RTL designs, gate-level implementations, and embedded bare-metal software and firmware
• Advanced techniques to eliminate large numbers of irrelevant faults without compromising the completeness of the verification, or the safety of the finished product

POSTER SESSIONS
4.3 UVM-FM: Reusable Extension Layer for UVM to Simplify Functional Modeling
4.4 Unraveling the Complexities of Functional Coverage: An Advanced Guide to Simplify your use Model
4.7 A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic
4.11 Managing and Automating Hw/Sw Tests from IP to SoC
4.12 Preventing Chip-Killing Glitches on CDC Paths with Automated Formal Analysis
4.14 Reusable UPF: Transitioning from RTL to Gate Level Verification
4.15 Hybrid Approach to Testbench and Software Driven Verification on Emulation
4.20 SoC Verification of Analog IP Integration through Automated, Formal-based, Rule-driven Spec Generation
4.26 Tired of Slow Gate Level Design Verification? Use these Efficient Modelling Styles and Methodology
4.29 Comprehensive IP to SoC Clock Domain Crossing Verification Using Hybrid Data Model
4.30 Cleaning Out Your Pipes – Pipeline Debug in UVM Testbenches
4.31 Improving Verification Predictability and Efficiency Using Big Data

EXHIBIT BOOTH #1101
Visit booth #1101 to see the latest Catapult, PowerPro, SLEC, Questa, Veloce, and Visualizer technology demos. Come discuss the very latest on UVM, Portable Stimulus, Formal, Emulation, Debug, VIP and much more with methodology experts including Harry Foster, Dave Rich, Tom Fitzpatrick, Neil Mullinger, Ben Whitehead, Ellie Burns, Jay Natarajan, and others. Don’t forget to enter to win our daily Amazon gift card drawing.

More blogs by Daniel Nenni