Blue Pearl adds RTL project transparency at #53DAC

You’re an RTL pro. You know what’s inside your code, and how many bugs you’ve tracked down and exterminated along the development path, and how much work remains. So, why did the meeting notice that just popped up asking for a monthly management project review presentation ruin your day?

For the most part, engineers would rather be designing than telling someone about what percentage of the design is complete and when it might be finished compared to the previously advertised schedule. “If you want it bad, you get it bad.” “The last 10% is always the hardest.” “It’ll be done when it works.” Insert more of the trite project manager repellant here. If you live in a -critical world where design quality matters more than anything, mid-course schedule questions often take a back seat until the finish line is in sight.

Truth be told, those are the kind of responses given in the absence of data. If an engineer has a good reputation for performance-to-schedule and quality and a modicum of openness when there are problems, management usually cuts them some slack. A month goes by, more work happens, the next project review meeting rolls around. Somehow the organization decides what is acceptable progress, and when to trust the remaining schedule enough to finalize a release-to-manufacturing plan everyone feels good about.

In a risk-adverse design environment, everyone goes nuts when there is a surprise. What actually constitutes a surprise depends on where it is viewed from. When a difficult milestone approaches, you probably know there is a good chance there could be a problem. Your manager might know about it, but their manager likely doesn’t, their peers are almost certainly out of the loop, and it is their opinion that counts in a public display of shocked-face in a project review.

Avoiding the shocked-face syndrome is a matter of instilling confidence, enough such that if some big surprise does happen, we did everything the organization knew how to do – it was a new-to-us problem, and we’ll work together to solve it. The right dose of transparency delivered succinctly on a regular basis can bring everyone together, and review meetings turn from management bashing to management actually helping.

We’ve introduced the concepts of RTL verification and debug including linting, CDC analysis, and timing constraints generation in previous posts (linked below) on Blue Pearl Software and their tool suite. At DAC 2016, Blue Pearl is introducing their new Management Dashboard tool as part of the Visual Verification Suite 2016.2.

The Management Dashboard provides a rapid visualization of the RTL verification process. Run-to-run information is captured providing evidence that issues have been engaged and solved. Graphical project reports highlight coverage, errors, warnings, and waivers updated from either interactive or batch runs. Presentation quality charts are generated in a few clicks from the same SQL database capturing all the verification data. Reporting is customizable, allowing teams to tune information for a higher-level project review or more detailed documentation.

For example, we’ve mentioned there is a sophisticated waiver management system in the Blue Pearl suite. As a project closes in on the finish line, there are likely still issues of varying severity being reported. These issues can be categorized as must-fix, won’t fix (for instance, a feature waived for schedule reasons), or otherwise waived, and the waivers charted over time. This helps with a clearer picture of progress; must-fix issues are documented and resolved, and other issues are identified and tracked with explicit visibility.

At DAC 2016, Blue Pearl Software is offering a close-up look at their Visual Verification Suite 2016.2 in private demonstrations – register in advance to reserve a spot.

Process matters, but only if you can show you’ve followed it. By being able to easily chart metrics on ASIC, FPGA, and IP RTL verification testing and issue resolution using the Management Dashboard, engineers can bring managers and collaborators into the loop quickly and move the discussion to specifics. This new level of project transparency helps everyone assess risk, quality, and schedules – and gets rid of project management spin.

More on the Blue Pearl verification suite:

• Tcl scripts and managing messages in ASIC & FPGA debug
• Cross-viewing improves ASIC & FPGA debug efficiency
• FPGA tools for more predictive needs in critical