Analog Bits Continues to Dominate Mixed Signal IP at the TSMC Technology Symposium

The recent TSMC Technology Symposium in the Bay Area showcased the company’s leadership in areas such as solution platforms, advanced and specialty technologies, 3D enablement and manufacturing excellence. As always, the TSMC ecosystem was an important part of the story as well and that topic is the subject of this post. Analog Bits came to the event with three very strong demonstrations of enabling IP on multiple fronts. Let’s examine how Analog Bits continues to dominate mixed signal IP at the TSMC Technology Symposium.

Demo One – New LDO, High Accuracy PVT Sensors, High Performance Clocks, Droop Detectors, and more in TSMC N3P

As more designs are going to multicore architectures, managing power for all those cores becomes important. The new LDO macro can be scaled, arrayed, and shared adjacent to CPU cores and to simultaneously monitor power supply health. With Analog Bits’ detector macros, power can be balanced in real time. Mahesh Tirupattur, Executive Vice President at Analog Bits said, “It is like PLL’s that maintain clocking stability we have are now able to offer IP’s to maintain power integrity in real time.”

Features of the new LDO macro include:

• Integrated voltage reference for precision stand-alone operation
• Easy to integrate, use, and configure with no additional components or special power requirements
• Scalable for multiple output currents
• Programmable output level
• Trimmable
• Implemented with Analog Bits’ proprietary architecture
• Requires no additional on-chip macros, minimizing power consumption

Taking a look at one more IP block for power management, Analog Bits’ Droop Detector addresses SoC power supply and other voltage droop monitoring needs. The Droop Detector macro includes an internal bandgap style voltage reference circuit which is used as a trimmed reference to compare the sampled input voltage against.

The part is synchronous with latched output. Only when the monitored voltage input has exceeded a user-selected voltage level will the Droop Detector output signal indicate that a violation is detected.

Below is a block diagram of an implementation. The composite Droop Detector comprises a primary Droop Detector, which includes a bandgap, plus additional Droop Detectors if needed by the application and which connect by abutment.

Demo Two – Patented Pinless PLL’s and Sensors in TSMC N3, N4 and N5

As discuss in this post, for gate-all-around architectures there will be only one gate oxide thickness available to support the core voltage of the chip. Other oxide thicknesses to support higher voltages are simply no longer available. In this scenario, the Pinless Technology invented by Analog Bits will become even more critical to migrate below 3nm as all of the pinless IP will work directly from the core voltage.

Examining the Pinless PVT Sensor at TSMC N5 and N3, this device provides full analog process, voltage, and temperature measurements with no external pins access required by running off the standard core power supply. This approach delivers many benefits, including:

• 

  No on-chip routing of the analog power supply
• No chip bumps
• No package traces or pins
• No PCB power filters

For voltage measurements, the device delivers excellent linearity as shown in the diagram.

Demo Three – Automotive Grade SERDES, PLL’s, Sensors, and IOs in TSMC N5A

As the electronic content in automobiles continues to increase, the need for a complete library of IPs that meet the stringent requirements of this operating environment become more important. In this demo, Analog Bits showcased a wide range of IP that meets automotive requirements on the TSMC N5A process.

I’ll take a look at Analog Bits’ Wide Range PLL.  This IP addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock multiplication to programmable clock synthesis for multi-clock generation.  This IP is designed for AEC-Q100 Automotive Grade 2 operation.

The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and IO devices. In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. Eliminating bandgaps and integrating all on-chip components such as capacitors and ESD structure helps the jitter performance significantly and reduces stand-by power.

The diagram below shows the block diagram for this IP.

Stepping back a bit, the figure below shows the various Analog Bits IP that is showcased in the N3P test chip demo at TSMC Technology Symposium. 

Executive Perspective

I had the opportunity to chat with Mahesh Tirupattur to get his comments on the recent announcements at the TSMC Technology Symposium. He said:

“The Analog Bits team is always innovating leading edge novelty IP solutions to solve customer design challenges on the latest processes.  Our mission is to enable integration of many off-chip components that reside on the board to on-die and soon on-chiplets. The benefits are significant by enabling embedded clocks, PMIC, LDO on-die – reduced form factor, costs, and improved performance with lower power. What is not to like about this? Our approach sets us apart in the marketplace as we truly add value by amalgamating system knowledge with leading edge mixed signal designs in advanced processes to enable new AI architectures.”

To Learn More

All of the Analog Bits demos from the TSMC Technology Symposium are now available to see online. If you missed the event, you can catch up on the Analog Bits demos here. You can also see all the TSMC processes Analog Bits supports here. It’s quite a long list. And that’s how Analog Bits continues to dominate mixed signal IP at the TSMC Technology Symposium.

 

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