Alphawave IP is Enabling 224Gbps Serial Links with DSP

Alphawave IP is a new member of the SemiWiki community. You can learn about the company and their CEO, Tony Pialis in this interview by Dan Nenni. Design & Reuse did a virtual IP-SOC Conference recently and Tony presented. The D&R event had a very strong lineup of presenters. They supplemented the prepared video presentations with two live panels on Automotive and FDSOI. This created a nice balance of prepared and live material, a good ingredient for a virtual event. Alphawave IP has a very strong portfolio of DSP-based multi-standard connectivity silicon IP solutions. They recently won the 2020 TSMC OIP Partner of the Year award for high-speed SerDes IP, so they’re definitely a company to watch. I was anxious to hear how Alphawave IP is enabling 224Gbps serial links with DSP at the D&R event.

DSP SerDes Introduction

Tony started by discussing the differences between an analog SerDes and a digital, or DSP SerDes. He explained that an analog SerDes can work reliably up to 36db NRZ or 30db PAM4. Since all equalization is implemented in the continuous time domain, this technology is sensitive to process variation. With a DSP-based design, most of the equalization is done digitally, allowing for more robust operation to 45db NRZ and 36db+ PAM4. This kind of design is also not very sensitive to process variation. Tony pointed out that the high-speed ADC required for a digital design like this is challenging to build.

Tony then went into some detail about analog linear equalization vs. DSP linear equalization. Clearly, the DSP approach is a better match for the demands of high-speed links.

The Road to 200Gbps Serial Links

Next, Tony discussed the challenges of getting from current 112Gbps PAM4 SerDes to 224Gbps PAM4 devices. Keeping the architecture the same, one can see that the reach for the device is dramatically reduced – roughly one inch vs. one foot. This is a serious challenge. The data is summarized in the figure below.

Given that package and board material aren’t likely to change much in the next couple of years, a new approach to increase data throughput for existing channels is needed. One that doesn’t suffer from the tradeoff issues shown above. Tony examined several alternative modulation schemes. Each has its own strengths and weaknesses relative to required channel bandwidth and signal-to-noise (SNR) ratio. He focused on PAM8 as a good candidate given its low channel bandwidth requirements. The various modulation techniques and their requirements are summarized in the figure below.

The next challenge to tackle is how to manage the SNR degradation of PAM8. One step toward a solution is to use a “maximum likelihood sequence detector.”  This advanced DSP detector uses an approach called Viterbi Detection to make data slicing decisions based on a sequence of data vs. on a single symbol which is the typical approach. This minimizes error across a sequence of symbols and results in an improvement in SNR of about 1-3 db.

Next, Tony focused on forward error correction (FEC). Using new, third-generation soft FECs based on approaches such as block turbo codes, one can recover over 10 db of bit error rate, thus compensating for the challenges of PAM8 further.

Summary

Tony concluded with an overview of Alphawave’s world-leading portfolio of DSP-based PHYs covering many protocols and applications, short and long reach. The portfolio is available and silicon-proven on TSMC 7nm and 5nm processes. With this technology platform, Tony sees a path to 224Gbps. If you’d like to learn more about Alphawave IP’s assessment of the future and how its technology fits, you can see Tony’s complete D&R presentation by registering here. He goes into a lot of detail. You can also visit the Alphawave IP website to learn more and find out how Alphawave IP is enabling 224Gbps serial links with DSP.

Also Read:

Alphawave IP and the Evolution of the ASIC Business

Demand for High Speed Drives 200G Modulation Standards

CEO Interview: Tony Pialis of Alphawave IP