HSPICE – I Didn’t Know That About IC Circuit Simulation

HSPICE is over 30 years old, which is a testimony of how solid the circuit simulator has been and how widely used it is. To stay competitive the HSPICE developers have to innovate or the product will slowly loose ground to the many other simulator choices. I listened to the webinar last week to find out what was new with HSPICE.

Szekit Chan was the webinar presenter and his title is HSPICE Staff Corporate AE at Synopsys.

User-specified Options can be used for your netlists, but first look at your .st0 file to see what all of the settings are. You can probably just remove these settings because the default values are now suitable for the vast majority of IC designs. I didn’t know that you could really safely remove the .options because they were usually set by some expert and we were told, “Don’t ever touch these settings or you will get the wrong results.”

The .lis file shows how much time it takes for: operating point, transient, etc.

Use a single option instead of all those individual options: .option RUNLVL = 1 | 2 | 3 | 4 | 5 | 6

1 – Fastest
3 – Default
6 – Most accurate

This approach of simplifying the speed versus accuracy tradeoff to a single number reminds me exactly of what HSIM uses, the hierarchical Fast SPICE tool. It certainly lowers the learning curve for a tool and doesn’t require an expert to experiment with arcane tool settings.

Remove the old convergence options, just let the built-in auto-convergence do its job instead.

If you have extracted netlists with thousands or millions of RC elements, then consider using the new RC Reduction: .option SIM_LA=PACT.This also works on files like SPF and SPEF.

Avoid probing all signals with v(*), be more selective instead. If you use v(*) then you tend to fill up the disk with too much data.

Want Results Faster?
Try Multi-core with HSPICE Precision Parallel (HPP) technology. One license uses two threads.

For Monte Carlo or corners use a compute farm. Use the “-dp” switch for distributed processing. Supports both SGE and LSF.

Some other options to speed up run times:

The summary of ways that you can speed up your long circuit simulation run times using command-line options or netlist statements:

During the Q&A time:

Q: Does RC reduction only apply to post-layout?
A: No, you can use it for both pre and post-layout.

Q: Any limitation on circuit size for HPP?
A: Not really, we’ve seen up to millions of elements.

Summary
The single biggest thing that I learned was that speed versus accuracy is now a simple integer in HPICE of 1 to 6, so good bye to the old way of tweaking .options for every different netlist topology. Using up to 8 cores to simulate a design looks very efficient, returning speed improvements up to 7.43X versus a single core.

Since the Magma acquisition announcement occurred on Friday after the webinar on Wednesday I’ve been thinking about the product overlap in the SPICE and Fast SPICE categories:

[TABLE] style=”width: 400px”
|-
| Product
| Synopsys
| Magma
|-
| SPICE
| HSPICE
| FineSim SPICE
|-
| Fast SPICE
| CustomSim
| FineSim Pro
|-

HSPICE has a much larger installed base because of its age however FineSim SPICE according to some offers better speed than HSPICE.

On the Fast SPICE side of things CustomSim offers hierarchical simulation and co-simulation with the Verilog simulator VCS, while FineSim Pro is a flat simulator with a less efficient co-simulation using the Verilog API. If you have a hierarchical design or need Verilog co-simulation then I’d use CustomSim.

It will be interesting to learn how Synopsys sorts out the new product roadmap in SPICE and Fast SPICE, hopefully by DAC they will have a story to tell us that makes sense. Possible scenarios are that:
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