The video and slides of the CEDA lunch from a month or two ago are now (finally) up here. Chris Malachowsky presented “Watt’s next.” Chris is one of the founders of nVidia and is currently its senior VP of research. He started by talking a bit about the nVidia product line but moved on to talking about supercomputers and their power requirements. Of course nVidia builds graphics chips that go in PCs and phones, but the basic parallel compute engine in those chips can be harnessed for other tasks. Given the title of the talk you won’t be surprised to know he spent most of the presentation on the challenges of power. Unless you’ve been under a rock for the last decade you have to know that power is one of the biggest challenges in chip design today. Computer architecture is one area that can make a big contribution along with all the techniques that have been developed at the SoC level. The microarchitecture can make an enormous difference. But moving data around is really a big problem: which uses more power, a 64-bit floating point multiply and add, or moving one of the operands 20mm across the die. Moving the data is already 5 times as costly, and by 10nm it will be 17x as costly (not to mention hundreds of times as costly to move it off chip). Science needs a 1000x increase in computing power but without requiring a power station to provide the power and remove the heat. The entire talkwas recorded on video and is synchronized with the slides.
He ended up talking about the department of energy program to build a 1000 petaflop computer (1 exaflop) and consuming “only” 20MW. By comparison we are currently at 2 petaflops consuming 6MW, so a 500X increase in speed for only a tripling of power. Click on the thumbnail to get a graphic that is large enough you can read the details.
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AMD acquires AI chip startup Taalas to boost inference performance by etching models into silicon
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Recent Forum Threads
Recent Article Comments
Intel and TSMC Take Different Paths to High-NA EUV
I still stand by this one: https://semiwiki.com/lithography/369490-asml-high-na-euv-is-not-ready-for-high-volume-production/— Daniel Nenni on August 8, 2026White Paper: The Semiconductor Foundation of Modern AI Data Centers
AI Chipsets are the latest Trendsetters— ambap851 on August 8, 2026Intel and TSMC Take Different Paths to High-NA EUV
"People keep ignoring EUV’s wavelength advantage is offset by stochastics hampering yield management. The higher NA just adds additional problems."…— Daniel Nenni on August 7, 2026Intel and TSMC Take Different Paths to High-NA EUV
People keep ignoring EUV's wavelength advantage is offset by stochastics hampering yield management. The higher NA just adds additional problems.— Fred Chen on August 7, 2026Intel and TSMC Take Different Paths to High-NA EUV
Thanks Daniel. I really appreciate getting the clarity. My guess, the tortoise wins. TSMC can cherry pick applications where HighNA…— Fred Stein on August 7, 2026Intel and TSMC Take Different Paths to High-NA EUV
Great article, Dan!!— John East on August 7, 2026ASML High-NA EUV is Not Ready for High-Volume Production
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Intel and TSMC Take Different Paths to High-NA EUV