The video and slides of the CEDA lunch from a month or two ago are now (finally) up here. Chris Malachowsky presented “Watt’s next.” Chris is one of the founders of nVidia and is currently its senior VP of research. He started by talking a bit about the nVidia product line but moved on to talking about supercomputers and their power requirements. Of course nVidia builds graphics chips that go in PCs and phones, but the basic parallel compute engine in those chips can be harnessed for other tasks. Given the title of the talk you won’t be surprised to know he spent most of the presentation on the challenges of power. Unless you’ve been under a rock for the last decade you have to know that power is one of the biggest challenges in chip design today. Computer architecture is one area that can make a big contribution along with all the techniques that have been developed at the SoC level. The microarchitecture can make an enormous difference. But moving data around is really a big problem: which uses more power, a 64-bit floating point multiply and add, or moving one of the operands 20mm across the die. Moving the data is already 5 times as costly, and by 10nm it will be 17x as costly (not to mention hundreds of times as costly to move it off chip). Science needs a 1000x increase in computing power but without requiring a power station to provide the power and remove the heat. The entire talkwas recorded on video and is synchronized with the slides.
He ended up talking about the department of energy program to build a 1000 petaflop computer (1 exaflop) and consuming “only” 20MW. By comparison we are currently at 2 petaflops consuming 6MW, so a 500X increase in speed for only a tripling of power. Click on the thumbnail to get a graphic that is large enough you can read the details.
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-
Apple’s Foldable iPhone Arrives at $2,000 as Supply Struggles to Meet Demand
latest reply by Xebec onstarted by Daniel Nenni on -
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latest reply by siliconbruh999 onstarted by user nl on -
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latest reply by MKWVentures onstarted by DanX on -
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started by karin623 on -
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Intel Nova Lake die shots show TSMC N2P being used for compute die, 18A-P for SoC Hub and Peripheral dies
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