In case you haven’t noticed, Synopsys has been in the press lately talking about their relationship with TSMC. Since I’m an internationally recognized industry expert they gave me a call for a briefing and I was happy to do it. Staying connected with the #1 EDA company is important and fun since I get to ask questions that most people don’t dare. Did you know that 90% of the 20nm tape outs used Synopsys tools? Not surprising at all. But first let’s set the stage here with what happened at the TSMC OIP conference earlier this month.
TSMC made a simulator company partner of the year for two reasons. One is modeling accuracy, which is key to silicon correlation, and two, simulation is now the center of the EDA universe. Case in point: SemiWiki hosted a webinar on Device Noise Analysis of Switched-Capacitor Circuits Webinar and it maxed out at 100 people very quickly. That’s a big number for a 4:30pm PST webinar. Simulation is king, absolutely. Unfortunately as design cycles shrink and mixed signal circuits are being forced down to leading edge process nodes, the simulation challenge is increasing and that spells opportunity for Synopsys.
The most interesting point of the conversation with Synopsys was about the Magma FineSim simulators. Not only are they actively supported, they are still in development. Customers love FineSim so this was big news to me. We also talked aboutHSPICE which is still the golden simulator for all of the foundries including TSMC and I don’t see that changing ever. HSPICE was my absolute favorite product when I worked for Avant!, people loved it and still do. Synopsys is also still supporting and developing Custom Sim, which includes the simulators that were acquired from Epoch and Nasda. Who knew?
The other interesting discussion was about the Laker tools. The Laker layout tool has now been married to the Synopsys circuit design environment. That means a much tighter integration to Synopsy simulation, definitely a win-win. Considering Cadence Virtuoso has 80%+ market share I’m happy to see a viable alternative from the #1 EDA company, absolutely.
We also discussed the IPL Alliance (Interoperable PDK Libraries), which is an industry standard organization established to develop an interoperable eco-system for custom design (iPDK). This has been the biggest disappointment for me as a Strategic Foundry Relationship Expert (my day job). The foundries support iPDK and the EDA companies support iPDK (with the exception of Cadence of course). The problem is the top semiconductor companies do not support iPDK and without customer demand it just isn’t going to happen. PDKs are a critical part of the fabless semiconductor ecosystem. Design starts are critical to the fabless semiconductor ecosystem. Open PDKs enable design starts. So what is the problem here?
As I write this I’m at the IEEE standards Symposium on EDA Interoperability (formerly EDA Interoperability Forum) with Paul McLellan. Paul ran the Virtuoso group at Cadence after the Ambit acquisition in 1999 so he should have much more to say about this.
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