Webinar: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff

I had the opportunity to preview an upcoming webinar from Synopsys on SoC Glitch Power – what it is and how to reduce it. There is some eye-opening information in this webinar. Glitch power is a bigger problem than you may think and Synopsys has some excellent strategies to help reduce the problem. The webinar is available via replay HERE.

The webinar is presented by Patrick Sheridan, PrimePower Product Marketing at Synopsys. I’ve known Pat for quite a while, dating back to the Cadence days in the 1990’s. Pat has substantial depth on the products and problems being discussed as he’s been at Synopsys for over 10 years. He’s also great at explaining things. Ashwin Sudhakaramenon, PrimePower Application Engineer at Synopsys handles the Q&A. Ashwin has been working as a designer and applications engineer on timing closure for multi-million gate designs for about 10 years, eight of them at Synopsys. Ashwin brings substantial technical depth to the table. These two gentlemen do a great job.

The topics covered in the webinar include:

• An introduction to the challenges posed by glitches on power
• Accurate glitch power analysis and optimization from RTL to signoff
• PrimePower case study examples
• Summary/Q&A

That’s a lot to cover in about 40 minutes. If you haven’t registered for the webinar yet, I’ll provide a bit of color on these topics to help you decide.

So, what is the glitch power problem? As designs become more complex and technology advances, the chance of switching activity due to a glitch increases. The problem shows up in all kinds of mainstream designs, including mobile and AI applications. Pat reports that the glitch power component for certain blocks in a design can range from 10% – 50%.  That’s not a misprint. Half the power could come from glitches.

These issues can also cause reliability problems from electromagnetic and voltage drop effects. To make it more challenging, designers need accurate vectors to predict where glitches may occur. It is best to fix these problems early in the design process, but detailed vectors are typically not available until late in the design process. Early in the process there is an RTL verification suite, but this data cannot yet take into account the detailed wiring delays, which is what causes the glitch. More challenges.

Once I heard all this, I had to watch the rest of the webinar and you will, too.

What follows is a close look at the technologies available to predict and mange glitch power from RTL all the way to signoff. There are three cornerstone capabilities required here:

• A signoff accurate power analysis engine (RTL to gate-level)
• Timing-aware activity delay shifting technology
• Generation of glitch-aware collateral

Pat goes into quite a bit of detail on each of these points, explaining why it’s important, what the impact on accuracy is and illustrating the results of the analysis. I don’t want to spoil the story – Pat is much better at explaining all this than I am and you really need to hear it directly from him.

The next section of the webinar provides details of four case studies using the Synopsys flow and in particular PrimePower RTL. The four case studies covered are:

• RTL glitch power source identification
• Gate-level glitch power from RTL fast signal data base (FSDB)
• Glitch-aware switching activity interchange format (SAIF) for power recovery
• Glitch-aware peak power for IR profiling

This section uses real customer design data at advanced process nodes, so the information is quite relevant.  A very useful Q&A follows that Ashwin handles quite well. That’s the summary of the webinar. By now, you must want to see the replay HERE.

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