Solido Has Perfected the Emerging EDA Company Business Model!

Last year at #51DAC we gave away more than a thousand printed versions of our book “Fabless: The Transformation of the Semiconductor industry.” This year we gave away pens with a light and stylus. My friends at Solido Design gave away 600 pens in their booth and we gave away another 400 at our DAC reception on Wednesday night. Solido was actually very clever about it. They turned on the lights and just left them in the trays on the counter. People came to them like moths to a flame… Even John Cooley stopped by to investigate! NO PEN FOR YOU! 😉

Speaking of clever, Solido is one of the more interesting companies I have worked with. They have perfected the emerging EDA company business model, absolutely. Solido CEO Amit Gupta is very approachable and I always enjoy talking to him. Here is an update from Amit and thank you again to the Solido booth staff for giving away our pens. It was greatly appreciated!

Q: What does Solido do?
We are the world-leading provider of variation-aware custom IC design software. Our customers are using our product, called Solido Variation Designer, to dramatically boost SPICE simulator performance by reducing the number of simulations and increasing design coverage for PVT, 3-sigma Monte Carlo, high-sigma Monte Carlo, hierarchical Monte Carlo and variation debug.

Q: How do your customers use your product?
We have 3 segments of users: memory, standard cell and analog/RF/custom digital designers. Our memory customers are using Variation Designer for full chip memory and cell level statistical verification. Standard Cell designers use our product for statistical verification and sizing of cell libraries. And our analog/RF and custom digital customers use Variation Designer for statistical & PVT verification and debug. Overall, users are getting improved design coverage in way fewer simulations than brute force.

Q: What industry trends are you seeing that impact your business?
We are seeing 2 big trends in the custom IC design space – continued move to smaller nodes and ultra-low power design at mature nodes. The move to smaller nodes is increasing variation. 28nm, FinFET and FD-SOI devices all have an increasing amount of variation impacting designs. Also, ultra-low power design at the more mature nodes, for applications like IoT wearables, is having larger variation impact due to lower supply voltage. Both of these trends have resulted in much more variation-aware custom IC design being done in the industry.

Q: What are the benefits of your customers using your product?
You can no longer cut corners when doing your SPICE verification. Increased variation causes designers to overdesign (poor power, performance and area) due to unnecessary over-margining, or underdesign resulting in poor yield. Our customers are using Variation Designer to see the impact of variation and eliminate unnecessary over and under design, so they get much better power, performance, area and yield.

Q: How is your business doing?
Our business is growing very quickly. We had 60% revenue growth last year, and 90% revenue growth in the first half of this year with increasing profits. We now have over 25 customers, including most of the top semiconductor companies, and over 1,000 users worldwide using our software regularly. We are also hiring – we have 10 software developer and applications engineering positions to fill immediately.

Q: What’s new at DAC this year?
We are pleased to be an invited presenter at the TSMC Open Innovation Platform Theater to showcase the Solido – TSMC integrated solution for our mutual customers. We also hosted a panel where engineers from Applied Micro Circuits, Cypress Semiconductor and Microsemi discussed their experiences using Variation Designer in their design flows and how they transitioned from legacy tools over to Solido.

In our demo suites, we are previewing our next major release – Solido Variation Designer 4.0. It includes Statistical PVT which delivers unprecedented accuracy and coverage across 3-sigma statistical variation and operating conditions, Hierarchical Monte Carlo which verifies full-chip memories with perfect statistical accuracy, and a suite of brand new features for memory, standard cell and analog/RF/custom digital designers.

Q: Where can our readers find more information about Solido?
They can visit our website at www.solidodesign.com for more product details and contact information. Or visit our careers site to see our job postings: http://www.solidodesign.com/page/jobs/