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Electronic Design Automation
Perhaps you’ve heard the term “clock gating” and you’re wondering how it works, or maybe you know what clock gating is and you’re wondering how to best implement it. Either way, this post is for you.
I can’t help but laugh when I watch a movie where the main characters are shrunk… Read More
Looking for better ways to search a huge state space in model checking, Ant Colony Optimization (ACO) is one possible approach. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always,… Read More
One of the harshest lessons we learned during the recent pandemic is the power of exponentials. As human beings, we are linear thinkers and can’t fathom how doublings of viruses — or technologies — can be destructive and disrupt everything. In my university classes and talks to business executives, I have always had to explain… Read More
A few times a year, I check in with AMIQ EDA co-founder Cristian Amitroaie to see what’s new with their company and the integrated development environment (IDE) market for hardware design and verification. Usually he suggests a topic for us to discuss, but this time I specifically wanted to learn more about the version of their Design… Read More
The last thing you want when taping out a design is to hit large numbers of violations in signoff checks that could have been flushed out and resolved in earlier flow iterations. For implementation flows (floorplanning, synthesis, place and route), it’s usual to do a lot of flow flushing work early in the design cycle and iteratively… Read More
The differences between commercial FPGA Prototyping (“Prototyping”) and Emulation have been well documented by the purveyors of commercial Prototyping and Emulation solutions, and the technical media. What has received less coverage is how Prototyping benefits differ from Emulation benefits. Both are intended to reduce… Read More
Whether it is the stock market or the semiconductor market, the name of the game is yield. In semiconductors, yield has to do with minimizing scrap costs in all phases of manufacturing. This means squeezing as many good dies from a wafer as well as maximizing the number of good assembled/packaged chips that pass system level testing.… Read More
Configurable processors are hot now, in no small part thanks to RISC-V. Which is an ISA rather than a processor, but let’s not quibble. Arm followed with configurability in Cortex-X. Both were considerably preceded (a couple of decades) by Synopsys ARC® RISC CPUs and CEVA DSPs. Each stressed configurability as a differentiator… Read More
Before chiplets arrived, it seemed like designing an electronic system was a bit simpler, as a system on chip (SoC) methodology was well understood, and each SoC was mounted inside a package, then the packages for each component were interconnected on a printed circuit board (PCB). The emerging trend to design a 3D IC using chiplets… Read More
Near the end of any large SoC design project, the RTL code is nearly finished, floorplanning has been done, place and route has a first-pass, static timing has started, but the timing and power goals aren’t met. So, iteration loops continue on blocks and full-chip for weeks or even months. It could take a design team 5-7 days… Read More
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TSMC Technology Symposium 2026 Overview