How IROC Makes the World a Safer Place with Unique Soft Error Analysis

I recently had an eye-opening discussion regarding the phenomena of soft errors in semiconductor devices. I always knew this could be a problem in space, where there are all kinds of high energy particles. What I didn’t realize is there are two trends that are making this kind of problem relevant on the ground as well as in space. The combination of advanced processes and reliability-critical applications makes the problem very real in everyday settings. Think functional safety for autonomous vehicles, medical devices and high-performance compute clusters. In all these cases, the glitches that result from a single event upset (SEU) and the associated soft errors simply cannot be tolerated. Let’s explore how IROC makes the world a safer place with unique soft error analysis.

My Discussion

I had the good fortune of spending some time with Dr. Issam Nofal recently. Many thanks to Minji Lee, sales director at IROC for setting it up. Issam has been with IROC for over 23 years, literally since the beginning. He has held positions such as Product Manager, Project Leader, and R&D Engineer. He holds a PhD in Microelectronics from Grenoble INP and has been leading the company for the past two years. You can learn more about this unique company in an interview with Issam on SemiWiki here. You can also learn about the risks related to soft errors in this piece by Minji Lee on SemiWiki.

What I focused on in my discussion with Issam was how IROC finds and helps fix soft errors in many types of circuits with a unique tool called TFIT® (Transistor Failure In Time). Not only did Issam explain how the tool works and what makes it unique, he also provided a live demo. Issam is clearly a very technical CEO – he understands the company’s products and its customers very well.

What’s the Problem?

The first part of my discussion was to delve into why exotic high energy particle bombardment is a problem in everyday settings here on Earth. We already covered the reasons why the problem isn’t limited to devices in space. Advanced semiconductor processes make circuits more sensitive to soft errors and the growing use of these circuits in reliability-critical applications demands protection against glitches of all kinds.

So, exactly what happens to create issues at sea level? Issam explained that neutrons resulting from cosmic rays interacting with Earth’s atmosphere make it to ground level. Approximately 13 neutrons per square centimeter at sea level and the concentration increases with altitude. So why is this a problem? Issam explained that, while neutrons are not charged particles, they can still hit the atoms of the silicon. This can create an atomic reaction that creates secondary ionizing particles, like those we find in space. Those particles can cause problems. In addition, impurities in chip packaging materials can create alpha particles, which are ionizing and can cause upsets if they hit sensitive transistors.

So, there are potential particle interactions that can cause event upsets and soft errors all around us. At this point in the discussion the phrase you can run, but you can’t hide came to mind.

Finding and Fixing the Problem with TFIT

Analyzing designs for soft error sensitivity can be a daunting process. You can certainly bombard a device with high energy particles using specialized equipment and see what happens. While this can be useful, it is a post-production test that requires high cost and expertise. Also, post-production means repair of any issues found will require a re-spin.

Pre-fabrication analysis can be done with 3D TCAD simulations. While this provides useful information during the design phase, calibration and use of these tools in the typical design flow can be quite arduous, time consuming and error prone. The good news is there is a better way from IROC.

TFIT is a best-in-class transistor/cell level soft error simulator. IROC’s foundry partners  develop models for TFIT based on an IROC-supplied methodology that uses simulation and calibrated measurements for a wide range of processes. Foundries also use the tool to optimize cell designs against soft errors. The TFIT methodology is based on foundry provided characterization models of ionizing particles for each technology node. These models are based on 3D TCAD simulations and actual measured effects of ionizing radiation from process test chips. The models are available for a range of process nodes from 65nm to N3 for TSMC, Samsung, GlobalFoundries, STM and IROC generic processes.

One of the unique features of TFIT is that it runs these models using a standard SPICE simulator.  This facilitates much simpler setup and much faster run times, making sophisticated soft error analysis available to any design team working on cell libraries (IP) or a custom chip. The installation is straight-forward and Issam explained that new teams are up and running after one to two two-hour training sessions. Hspice, Eldo, Spectre, and Finesim are all supported.

TFIT essentially democratizes advanced soft error analysis, making this important optimization step available to all design teams. Issam shared the figure below to illustrate the TFIT flow.

Issam provided an overview of some of the main soft error analysis that is available with TFIT. The list is quite comprehensive:

• Critical charge computation
• Cross-section computation
• Angular heavy ions impact simulation
• Neutron SEU/SET FIT computation
• Alpha particles accelerated testing simulation
• Neutron MCU FIT and patterns computation
• Thermal neutron SET/SEU computation

Issam then showed me how TFIT can be used to analyze design sensitivity to soft errors. The figure below shows how TFIT data can be overlaid on the actual circuit. What you see here is the areas of the design that are sensitive to particles of various energy levels, shown on the right side of the diagram as linear energy transfer (LET) values. Areas that are sensitive to lower energy particles are more likely to cause issues since lower energy particles are more likely to occur.

Armed with this kind of information, remediation can be added to the design to reduce sensitivity to soft errors. Issam explained that this typically takes the form of adding redundant copies of the sensitive circuits and using arbitration logic to monitor outputs to determine if a soft error occurs. In this case, the redundant logic can be used and circuit behavior is not interrupted. Note the separation of redundant circuits is also a consideration to ensure a soft error doesn’t impact more than one of the redundant circuit elements due to proximity.

The work involved here can be quite detailed. The good news is that TFIT is easy to use and runs fast so iterations can be done in a time and cost-efficient way.

Issam went on to show many more design techniques to reduce soft error sensitivity; approaches such as memory interleaving is one example. While the effort can seem large, the payoff is quite important. For the types of applications discussed, the interruption generated by soft errors cannot be tolerated. IROC has fast, easy to use tools, extensive experience and a broad set of foundry relationships to help you achieve this important goal efficiently.

The figure below illustrates the results of some of this work.  In this case, the plot on the left shows significant areas of the circuit that are sensitive to high-energy particles. The plot on the right shows the results after layout optimization – with much smaller areas of sensitivity. 

To Learn More

If you are developing products for high-availability applications, getting to know how IROC can help you succeed is a must. You can find out more about the unique TFIT tool here. And that’s how IROC makes the world a safer place with unique soft error analysis.