Increase Your Chip Reliability with iROC Tech

As we have moved towards extremely low process nodes with very high chip density, the cost of mask preparation also has become exorbitantly high. It has become essential to know about the failure rates and mitigate the same at the design time before chip fabrication, and also to make sure about chip reliability over time as it is constantly exposed under cosmic rays and natural environment of radiation. Chip failure due to soft errors can prove to be costly in systems where human safety is of utmost importance such as medical, automotive, aerospace etc.

Although I had read about iROC tools (TFIT, SOCFIT) for detecting Soft Errors and methods for mitigating the same; last week was a fortunate time when I came across a webinar, moderated by Paul McLellan from Semiwiki and presented by Adrian Evans, Principal Engineer from iROC.

This was a nice opportunity to know all about Soft Errors, their causes, impact on chips and systems, prediction and cure. So, what is the source of soft errors? As evident from the following picture, they are caused due to neutron particles present in nature and impurities in packaging material emitting alpha particles.

These alpha particles can upset charge at particular points in the circuit and cause temporary logic failure as shown in figure below.

How is Soft Error Rate (SER) expressed? It’s in terms of Failure in Time (FIT), i.e. 1 failure in 10[SUP]9[/SUP]hrs. Considering 10s of chips in a system and 100000s of systems in the field, the number of soft errors in a week or month can be significant. Trends show that at SoC level at lower nodes, as the number of transistors multiplies the SER increases many fold with multi cell upsets.

So, how to avoid soft errors? What’s the cure? Many times there are masking effects which block soft errors. Below are examples of low level masking.

Also, there are high level functional masking (inverted pixel or corrupted frame in video applications, corrupted packet in networking application etc.).

As soft errors are more prone in FFs and Memories, there are specific techniques to remove those. In case of memories, standard procedures with Error Correcting Codes (ECC) and other techniques are used. For FF, hardened Flip-Flop designs are made.

How to detect the soft errors? That’s an expensive proposition. The chip has to be tested for its sensitivity to radiation. iROC provides radiation testing services. It can test sensitivity to alpha particles in-house using a radioactive substance.

Soft errors can occur at cell, circuit, or system levels under any user environment. iROC has special tools to detect them at design time before manufacture.

TFIT is transistor level soft error simulation tool, suitable for library designers and SOCFIT is circuit level tool for chip architects. TFIT uses SER response models supplied by foundries on circuit design (SPICE netlist, GDSII), runs circuit simulation and generates FIT rate for each cell for the designer to find the weakest transistors. Similarly, a weak chip in the system can be determined and worked upon for improvement or replacement. As SER data can vary with voltage, logic state and StdCell; it’s desirable to get SER data in terms of error bars from the foundry.

In the overall eco system, iROC is well connected with Foundries (GF, TSMC), fabless design companies (for SER analysis and simulation during design), Radiation Test Facility, System houses and IP suppliers (for radiation testing services).

It was an interesting session keeping me engaged throughout to know about what next. A listening to the detailed presentation can be attended at the recorded link here.