Methodology to Minimize the Impact of Duty Cycle Distortion in Clock Distribution Networks

Synchronous circuits dominate the electronic world because clocking eases the design of circuits compared to asynchronous circuits. At the same time, clocking also introduces its share of challenges to overcome. No wonder, a tremendous amount of time and effort have been spent over the years on developing and implementing various types of clock distribution networks. A lot of time has also been spent on analyzing and addressing clock jitter due to power supply. And at the design level, a lot of thought goes into choosing the clock duty cycle when designing a circuit.

In terms of accuracy, SPICE simulations have always been held as the gold standard. But SPICE simulations are compute-time intensive and typically run on just small portions of a design.  Instead, gate level simulation was used as the default signoff tool for chips until the turn of the 21^st century. This worked well as most of the designs then were not very large or complex and the process nodes in use were 250nm or larger. As process nodes advanced and design size and complexity started growing, gate level simulation as a signoff tool started getting strained. Static timing analysis (STA) took over as the default signoff tool and has worked well for the last two decades. But today’s advanced-process-based designs are facing chip-signoff challenges due to limitations of STA and duty cycle distortions (DCD). While the intrinsic limitations of STA were always present, they did not pose practical issues when it came to signoff on less advanced process nodes. And while duty cycle distortions go hand in hand with clocking, they were either corrected with a DCD correcting circuit or were not serious enough to impact the proper functioning of a design. But no longer.

We’re entering an era where STA needs to be augmented for addressing DCD and increasing verification coverage for high confidence at chip signoff. Wouldn’t it be great if overnight simulation runs on multi-millions of gates can deliver SPICE level accurate results? Infinisim has published a whitepaper that explains how their analysis tools and methodology can deliver all of the above. This blog covers the salient points from that whitepaper.

Duty Cycle Distortion (DCD)

Duty cycle distortion (DCD) is a propagation delay difference between low-to-high and high-to-low transitions of the clock and is typically expressed in percent. With 7nm and below, deep clock distributions are prone to DCD accumulation as the signal propagates through different levels. With millions of gates on a single clock domain, even a picosecond DCD per gate will add up to significant distortions at the end points. While DCD results from manufacturing process variations, marginal designs and electrical noise, it gets worse with transistor aging. Traditionally, duty cycle correcting circuits have been added to designs to remedy the problem.

Duty Cycle Correcting Circuit

Duty cycle corrector circuits work by adding or removing delay from the rising or falling transition until an expected duty cycle is reached. While duty cycle corrector circuits may help reduce DCD, they add complexity to the clock design of today’s already complex chip designs. With time to market pressure ever increasing, the goal is to reduce complexity wherever one can in order to get the chip out on schedule. Implementing a methodology that accurately analyzes DCD can eliminate the need for DCD correcting circuit and reduce the complexity of a design.

Limitations of STA

STA tools do not compute the full clock signal waveforms. Instead,  they estimate timing values by inferring them from pre-characterized timing libraries for different PVT corners. While this makes STA fast, it is not accurate enough at finer geometries, failing to detect DCD and rail-to-rail failures directly.

At sub 7nm designs with higher transistor nonlinear effects, increased aging and deep clock distributions, complex analysis is not possible with traditional STA. In addition, STA is especially inaccurate for advanced clock topologies containing meshes and spines. In essence, DCD, rail-to-rail and minimum clock pulse width problems are critical issues that can go unnoticed during STA, resulting in serious failures in silicon.

Infinisim’s ClockEdge

Infinisim’s ClockEdge is a high-capacity, high-performance, SPICE accurate, end-to-end integrated clock analysis solution. ClockEdge can handle chips that incorporate multiple topology high-speed clocks and used for full-chip sign-off. It plugs into current design flows, allowing designers to simulate large clock domains with millions of gates.

Overnight Runs on the Gold Standard

Infinisim’s ClockEdge computes DCD using SPICE simulations of an entire circuit using full interconnect parasitics. The simulator identifies the nets that are failing duty cycle, minimum pulse width and rail-to-rail failures. It generates clock waveforms and estimates the maximum frequency at which rail-to-rail failures occur. SPICE accurate results are delivered overnight on clock domains containing 4+ millions gates, which is unheard of in standard SPICE simulations.

High Verification Coverage

Designers can run multiple PVT corners and input duty cycles for comprehensive and increased design verification coverage thereby gaining high confidence in their design. ClockEdge users routinely find DCD issues missed by STA-based-CTS methodologies.

Some Salient Features of ClockEdge

• • SPICE accurate results overnight, for clock domains containing 4+ million gates
  • Leverages distributed computing to simulate and analyze large complex clocks
  • Handles complex clock topologies includes trees, grids/mesh and spines
  • Reports include timing, process variation, power and current analysis
  • OCV analysis: during design for guard-band reduction, in post-design phase to estimate yield
  • Results from ClockEdge are integrated into CTS flow for optimizing design

Some use cases below where ClockEdge augments STA for SPICE accurate, comprehensive timing analysis:

• • Timing optimization during design iterations
  • Base-layer tapeout/Metal-layer tapeout signoff verification
  • Post-fab investigation into performance degradation and potential improvements for next revision

Rail-to-Rail Failures Report

ClockEdge also reports rail-to-rail failures by plotting the maximum and minimum voltages reached by every node in a full clock domain. The Figure below shows ClockEdge identifying a gate at level 1 failing to reach supply voltage of 1.1v.

Fmax Report

The data can also be represented in a Fmax plot to show the expected maximum frequency (Fmax) at which rail-to-rail failures would occur for each node. Refer to the Figure below.

The above reporting capability allows designers to quickly determine if there are any rail-to-rail failures amongst the millions of nodes on a particular clock path.

Summary

ClockEdge delivers SPICE accurate results on clock domains containing 4+ millions gates and higher verification coverage compared to competitive products in the market. It easily plugs into current design flows used by customers. And it can accurately analyze top-level, block-level and hard-macro level clocks to cover all blind spots. The tool finds DCD, jitter, aging and rail to rail issues that are routinely missed by traditional STA-based methodologies.

For more details about ClockEdge, you can access the whitepaper here.

To learn about a comprehensive solution for full-chip clock analysis, visit Infinisim.

Also Read:

WEBINAR: Challenges in analyzing High Performance clocks at 7nm and below process nodes

WEBINAR: Overcome Aging Issues in Clocks at Sub-10nm Designs

White Paper: A Closer Look at Aging on Clock Networks