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Is my Library or Semi IP really OK to use?

Is my Library or Semi IP really OK to use?
by Daniel Payne on 05-10-2013 at 11:42 am

The tremendous growth in IC and SoC design complexity has now enabled engineers to place bilions of transistors on a single chip. To make that growth possible design teams resort to using libraries and semi IP provided by other groups in their company, or outside IP vendors. To lower risk, you must know that the IP being used in your next SoC is correct and that no errors are present.

You could create some incoming tests on your re-used IP, or maybe even buy some Verification IP (VIP). There’s a three year old EDA start-up called Fractal Technologies that has a tool that help you test the quality of IP by:

  • Reporting mismatches or modeling errors for Libraries and IP

    • Do all schematic pins occur as terminals in layout and abstract views?
    • Are all delay arcs from Liberty present in Verilog?
    • Can all pins be routed in first-metal?
    • Is a reset pin active-low in SPICE, Verilog, and .lib files?
    • Does the LEF abstract correctly cover the layout view?
    • Do all cells abut?
    • Check on presence and contents of cell- or pin-properties?
    • Verify that certain pins are located correctly within a cell?
  • Checking view consistency (ECSM, CCS)

    • Are CCS peak currents increasing with capacitance?
    • Are cell delays increasing with increasing temperature and decreasing supply voltage?
  • Checks occurence and correctness of cells, pins and terminals
  • Cross-checks delay tables, delay path conditions, setup and hold-times
  • Checks consistency of Liberty characterization data
  • Checks routability requirements on cell terminals
  • Checks functionality descriptions
  • Checks layout representations
  • Checks can be coded by end-users in popular scripting languages

This checking technology is called Crossfire and it works with industry standard formats:

  • LEF, DEF
  • GDS II, Oasis
  • CDB
  • OA (Open Access)
  • Milkyway from Synopsys
  • Verilog, SystemVerilog, Verilog AMS, VHDL
  • PLIB
  • Timing Library Format
  • FastScan, Tetramax
  • STIL/CTL (Core Test Language)

If you are a group that creates or uses Libraries or semi IP, then using this technology would improve your quality in a shorter time.

At DAC you can see the folks at Fractal Technologies in booth #1617, ask for Rene Donkers.

lang: en_US