WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 598
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 598
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)
            
14173 SemiWiki Banner 800x1001
WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 598
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 598
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)

Advanced Node Design Webinar Series

Advanced Node Design Webinar Series
by Daniel Nenni on 10-14-2012 at 8:15 pm


At advanced process nodes, variation and its effects on the design become a huge challenge. Join Cadence® Virtuoso® experts for a series of technical webinars on variation-aware design. Learn how to use advanced technologies and tools to analyze and understand the affects of variation. We’ll introduce you to the latest Virtuoso techniques, best practices, and methodologies you can use to design and verify your advanced node designs.

REGISTER NOW

In these concise 1-hour sessions, we’ll address hot topics including:

  • How variation affects design performance at advanced process nodes
  • Advanced technologies and tools to analyze and understand the affects of variation
  • Using sensitivity analysis to identify devices and parameters that impact circuit performance
  • Using optimization techniques to tune design performance and meet specs across the operating conditions
  • Using worst-case corners analysis to narrow the number of corners against which the design needs to be verified
  • How to use high-sigma yield analysis to predict up to 6 sigma yield
  • Layout-dependent effects (LDE) on circuit functionality at advanced process nodes
  • Using LDE analysis technologies to detect, mitigate LDE effects at the early phase of the design and reduce design iterations

These webinars are methodology- and application-based. Plus, you don’t need to travel—you can view these presentations and demonstrations from the comfort of your home or office!

Nov 7, 9:00am PT Variation-Aware Design: Understanding the “What If” to Avoid the “What Now”

In this webinar, we will define variation, how it affects design performance, and what you can do to analyze, understand, and limit these effects. We’ll demonstrate how to use sensitivity analysis to identify devices and design parameters that impact circuit performance, and how to use sensitivity analysis results to tune and improve design robustness.

Nov 14, 9:00am PT Variation-Aware Design: Efficient Design Verification and Yield Estimation

In this webinar, we’ll show you how to use advanced capabilities, such as worst-case corners and high-sigma yield analyses, to efficiently cover the design space and estimate design yield.

Dec 5, 9:00am PT Variation-Aware Design: Detecting and Fixing Layout-Dependent Effects using the Virtuoso Platform

In this webinar, you’ll see how advanced Virtuoso technologies can help you detect and fix LDE problems by rapidly producing layout and verification results that feed the industry’s first LDE-aware design flow. Learn how to fine-tune the corrections necessary to make sure LDE problems don’t stop you from getting your design manufactured on time.

Register now: https://www.secure-register.net/cadence/SILR_VAD_4Q12

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