I recently had a call with Rob Dekker, Founder and CTO of Verific. If you’re in EDA or semiconductor CAD, chances are high that you know who they are. They’re king of the hill in parser software for SystemVerilog and VHDL. When you hear a line like that, you assume a heavy dose of marketing spin, but here it really is fact. I don’t know of anyone else in this line with their market presence. They’re used by all the EDA majors and by CAD groups in leading semiconductor and systems companies (Intel and Google, to drop a couple of names).
I have some familiarity with this space since I was for a short time in Interra Systems before we spun out as Atrenta, and Interra provided our Verilog and VHDL language parsers. I don’t know about the business side of that activity but I do know we were always struggling to keep up with the standards and, more challenging, vendor-specific wrinkles on those standards. When you’re low in the EDA value chain and you’re using your own parsers, that’s a constant headache in competing with the big tool providers. Using Verific for parsing eliminates those headaches and lets you focus on your differentiating value-add.
I asked Rob what got them started on this path. He had been responsible for language front-ends for the Exemplar logic synthesis software back in the 1990s. In 1999, after Exemplar was acquired by Mentor Graphics, he decided to start his own company. He was originally thinking about developing a formal verification tool (hence the name Verific), but of course had to start with language parsing and RTL elaboration, the front-end to any formal tool. So he built that and found several customers who were interested in licensing that software.
A couple of years later, a company developing an equivalence checker approached him wanting to license the parsers. That was one of those defining forks in the road for a small company – if he continued along the path he originally planned, we would be competing with a customer. Instead he decided to stay in the parser business but do the very best he could in that domain. The formal company became a customer and fairly quickly after that most formal providers were using Verific parsers.
The business model is a little unusual but seems to work well for them and for their customers. They were clear from the outset that they wanted to be in the (software) IP business, not the services business, but that they would license source-code rather than compiled libraries. Customers can build on their favorite hardware/OS platforms, as best suits their needs. Of course if you have source code, you can change it. The model here seems to be that you’re likely only to make minor tweaks. Verific will support these changes, merging them on top of a standard release and re-regressing with their test suites before release back to the customer. Rob says that customers like this model. In the event of something bad happening to Verific, customers already have hands-on experience with the source-code, a possibility which remains theoretical in most software license agreements.
The pricing philosophy is equally simple; this has to be 50% of what the customer thinks it would cost them to develop. Customers are always optimistic when they do this calculation. So the real percentage has to be 25% of Verific’s development cost, which means they have to sell 4 copies before they start to make money. Turns out that their customers find this very reasonable, so they don’t run into a lot of resistance.
You’re probably wondering about the available market for products like this. Rob said that they originally mostly targeted EDA developers, for formal, synthesis, some simulators, hardware accelerators, even virtual prototypers. The Verific software is built in C++, with C++ interfaces, so is a natural fit for that type of development. They still find some new business in this area but have seen more growth over time in semiconductor CAD groups, in traditional semis and in design groups in the big systems houses. There’s still need for a lot of custom tooling in these groups and Verific provides a good turnkey front-end to RTL analysis.
However, in-house CAD groups are generally not as enthusiastic about C++ development; their development languages of choice tend to be Python or Perl. Verific’s first pass at meeting this need was to wrap underlying C/C++ APIs for these languages. I’ve been there, done that so can sympathize with Rob’s statement that this didn’t help so much. APIs for these kinds of applications tend to be overwhelming. You can do anything you want to do, but it takes forever to figure out how. In 2017 Verific solved this problem by acquiring the INVIO platform from Invionics. INVIO builds on top of the basic APIs with a much simpler object-based model and the kind of lookup functions you’d expect to have in a Tcl interface. I’d imagine this is a big hit with CAD developers and probably even with designers.
Asking Rob about long-term goals, I got an answer you’d never hear in Silicon Valley, perhaps because this is a company with strong European roots. Rob feels they are in a good niche market; they are already the industry standard with little competition, they like where they are and don’t feel the need to grow too fast. Which is just as well, because he doesn’t see massive room for growth. They have been able to manage double digit growth each year, which is fine by them, helped along now and again by a new parser, such as a recent introduction for UPF.
In an industry where CAGRs must be spectacular and competition is a blood sport, this is a refreshing change. Rob told me the reason they chose a giraffe as a logo was that it has a good overview of its surroundings, but at the same time has a gentle and non-aggressive nature both internally and with partners. Quality of life as a primary goal – an interesting differentiator.