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EDA
Posted on by Paul McLellan

Fast Track your SoC Design

Fast Track your SoC Design
by Paul McLellan on 08-17-2011 at 5:24 pm
Categories: EDA

Atrenta has four seminars coming up on SoC realization. More and more design is actually about finding IP and integrating it together at the block level, and then handing it off to a standard RTL to GDSII flow. The three focus areas are:

  • finding quality IP faster
  • accelerating IP integration and SoC assembly
  • handing off RTL successfully.

The seminars are at:

To register, click on the city name above for the location that you want to attend. And if you fill out your survey at the end of the event you could win an iPad.

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