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WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4037
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4037
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
)

Expansion at Calypto through Real Value Addition in SoC Design

Expansion at Calypto through Real Value Addition in SoC Design
by Pawan Fangaria on 09-22-2014 at 1:00 pm

When we get the notion of expansion of a company, it always provides a positive picture about something good happening to boost that expansion. There can be several reasons for expansion such as merger & acquisition, formation of joint venture or partnership, large customer orders and so on. However, organic expansion which happens due to real value addition into the products that drives customer demand and satisfaction brings eternal cheer and confidence among company’s workforce leading to ever increasing value of the products and the company’s general ecosystem.

These are the thoughts which came to my mind when I met Sanjiv Narayan, VP & Managing Director at Calyptoin its Noida office. Sanjiv has been a good friend of mine since my Cadence days; I admired his knowledge of synthesis, optimization and verification domain. He heads Calypto’s Noida site which has a strong committed workforce of about 60 people; 90% of the workforce is involved in R&D development, that’s quite impressive. Since we had met after a while, we had a long conversation on several aspects; I am summarizing some of the prominent ones below.

Accommodating the current team comfortably and looking forward to further expansion driven by growing adoption of their products, Calypto has already moved (this is the third time in last ten years) to a new facility equipped and ready to accommodate a larger team. The India team provides major R&D support to all product lines of Calypto. Sanjiv expects the new office to be able accommodate an additional 50% growth in headcount and Calypto is already aggressively hiring for R&D and Application Engineering positions in India. Calypto is seeing rising business and increased usage of their tools in Asia Pacific (AP) region. They already set up an office in Korea earlier this year to support Calypto’s Korean customers. The expanded Application Engineering and Services workforce in Noida will support the entire AP region. Calypto is also setting up an office in Bangalore – it should be operational before the end of the year.

So, what’s driving this expansion? Of course, Calypto has a pioneering product portfolio at system and RTL level coupled with the semiconductor industry’s unique formal verification technology; Catapult HLS tool, PowerPro power optimization tool at RTL level and SLEC sequential equivalence checker. What’s unique about them – Catapult can synthesize hardware descriptions written in either C++ or SystemC to RTL, no proprietary or specific standard is needed; PowerPro is reported to provide the best power saving in the industry with functionally clean RTL proven at the gate level; SLEC is the most versatile formal verification tool that can accurately check (through its unique sequential equivalence checking capability) equivalence between C++/SystemC and RTL (SLEC HLS) and RTL and optimized RTL (SLEC RTL and SLEC Pro) which may be obtained either manually or through the use of PowerPro.

Naturally, Calypto is gaining customers’ attention, increasing customer base and seeing consistent growth in its revenue over the years with top semiconductor companies using their products. To know more about their products/technologies and general technical learning, attend some of the upcoming events where Calypto is presenting –

Sep 25, 4:00 PM – 5:30 PM atDVCon India in Bangalore

Tutorial on “Low Power Design & Verification Using HLS” to be presented by Sanjiv Narayan, Sandeep Dagar, Vikas Tyagi and Vishal Sinha

Oct 1-2, 11 AM – 6 PM atARMTechCon in Santa Clara Convention Center, CA

Exhibit at Booth #715

Also read:
Accelerating SoC Verification Through HLS
How to Reduce Maximum Power at RTL Stage
Designing the Right Architecture Using HLS

More Articles by Pawan Fangaria…..

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