Accellera Update at DVCon 2023

I have a new-found respect for Lu Dai. He is a senior director of engineering at Qualcomm, with valuable insight into the ground realities of verification in a big semiconductor company. He is on the board of directors at RISC-V International and is chairman of the board of directors at Accellera, both giving him a top-down view of industry priorities around standards. Good setup for a talk with Lu at DVCon’23, to get an update on Accellera progress over the last year. The executive summary: work on a CDC standard is moving fast, there are some updates to IP-XACT (IEEE returning the standard to Accellera for update), IPSA (the security standard) is now moving towards IEEE standardization, and safety and UVM/AMS are still underway.

Lu also talked a little about Accellera/IEEE collaboration. Collaboration is valuable because IEEE standards are long cycle (5-10 years) and ultimately definitive in the industry, whereas Accellera can iterate faster to a 90% convergence in a smaller group, leaving the last 10% for IEEE cleanup. Obviously valuable when a standard is first released but also in updates. On major updates IEEE often returns control to Accellera for spec definition/agreement. When ready, Accellera passes the baton back to IEEE and the Accellera working group folks join the IEEE working group for a smooth transition.

PSS

PSS is gaining significant traction for system level testing, witness applications from most tool vendors. Active standard development is now on the proposed 2.1 release. The big news here is that they are dropping support for C++. Apparently, the demand for C++, originally thought to be a good idea (maybe for SystemC?), just isn’t there. Demand for C support continues strong, however. Since this is a big change, the working group isn’t yet sure if they should rename the release 3.0. Still in debate.

There are other plans for 2.1/3.0, including more on constrained random control coverage. Lu didn’t want to share more than that. I bet as a verification guy he knows more, so probably still under wraps.

Functional safety and security standards

The objective of these standards is similar, to ensure interoperability between different vendor solutions, from IP level design up to SoC level design. And in the case of safety, to enhance propagation of constraints/ requirements from OEM/Tier1 needs down to the design, and constraints added in the design back up to the ultimate consumers of the functionality. (Perhaps that principle will also apply at some point to security standards, but I guess we need to walk before we can run.)

IPSA is underway to IEEE standardization as mentioned earlier. The functional safety standard is still in development. Lu told me that he expects a white paper update around the middle of the year, followed soon after by a draft standard.

CDC and IP-XACT

The goal for CDC is to standardize constraints and other meta-data between vendor platforms. Lu made the interesting point that all the vendor CDC products do a good job, but interoperability is a nightmare. That is important because no tool can do full chip CDC on the big designs. The obvious answer to the full chip need is hierarchical analysis, but IPs and subsystems come from multiple internal and external suppliers who don’t necessarily use the same CDC tools.

CDC products are mature and users have been complaining long enough that the working group apparently knows exactly what they have to do and have set an aggressive schedule for their first release. Lu expects this one to cycle fast. There might be some deficiencies in the first release, such as a lack of constructs for re-convergent paths, but the bulk of the constraints should be covered.

For IP-XACT, Lu expects most updates to be in reference models and documentation. In a quick scan through slides from the DVCon tutorial, I saw several improvements to register map and memory map definitions. I wouldn’t be surprised if this was also in part a response to divergences between vendor solutions. Or perhaps too many vendor extensions? I also saw support for structured ports for cleaner mapping from SystemVerilog for example.

UVM AMS

This standardization effort is a little more challenged. The standard depends on progress both in UVM and in SystemVerilog AMS extensions. For UVM, the working group has made pretty good progress. More challenging has been syncing with IEEE on AMS SystemVerilog language requirements. This appears to be an administrative rather than a technical problem. System Verilog, IEEE 1800, is an established standard and IEEE updates such standards every 5 or 10 years. The working group AMS proposals for System Verilog were maybe a little too ambitious for IEEE deadlines and a scale down effort took long enough that it missed the window.

I’m sure no-one wants to wait another 5 years, yet vendors are unlikely to update their support until they know the standard is official. Lu tells me there are a number of ideas in discussion, including using the 1880.1 standard, originally intended for AMS but never used. We will just have to wait and see.

Membership and Recognition

Lu had an interesting update here on growing participation from Chinese companies. China has participated actively for standards like 4G and 5G, but EDA/semiconductor company participation in standards has not been a thing. Until this year.

Lu’s read is that Chinese companies take the long view. Embargos come and go but design must continue. Those companies will have to work within a standards-compliant ecosystem, so they feel need to be active in understanding and helping define standards.

Huawei has been an associate member for a while. New associate additions in EDA include Univista and X Epic. A semiconductor associate addition is ZEKU, Oppo’s semiconductor subsidiary. If you’re not familiar with Oppo, their product line includes Vivo smartphones, very popular in India and Europe and now starting to appear in the US.

Also of note, in this DVCon, Accellera honored Stan Krolikoski by establishing an annual scholarship for EE/CS undergrads. Lu acknowledged, this has an additional benefit in promoting coursework on standards at the undergraduate level. Accellera also presented the Technical Excellence award posthumously to the late Phil Moorby of Verilog fame. Well deserved.

Lots of good work, more good stuff to anticipate!