Clock Aging Issues at Sub-10nm Nodes

Semiconductor chips are all tested prior to shipment in order to weed out early failures, however there are some more subtle reliability effects that only appear in the longer term, like clock aging. There’s even a classic chart that shows the “bathtub curve” of failure rates over time:

If reality and expectations don’t align in the wear out region, then the financial impact of recalling chips embedded inside of systems can cost millions of dollars or even cost human life in safety critical applications.

A 7nm SoC can have 10 billion transistors, and to meet the power spec there are many clock domains, and multi-voltage power domains; resulting in aging issues like jitter, duty cycle distortion, insertion delay, reduced design margins, and increased process variation. To predict the impact of transistor aging requires knowing the circuit topology, switching activity, voltages and even temperature – a complex goal.

Transistor aging comes about from a few effects: Hot Carrier Injection (HCI), Negative Base Temperature Instability (NBTI), Positive Base Temperature Instability (PBTI). Hotter temperatures accelerate these effects. The duty cycle impacts BTI effects, and frequency has a proportionate effect on HCI. With HCI there are charges that get trapped in the oxide layer of the transistor, changing the Vt of the devices permanently. The BTI effect is higher than the HCI effect for 7nm nodes, as shown in this chart of insertion delay, where the black line is a fresh circuit, while aging effects from HCI are orange, and BTI effects are in blue.

IC design methodologies above 10nm used Static Timing Analysis (STA) and some SPICE simulations of the clock, along with guard-banding for parameters like jitter. Aging could be applied across all devices to provide an idea of the electrical and timing impacts.

Under 10nm designs require a more comprehensive analysis of clock aging impacts, and Infinisim has created a tool called ClockEdge that analyzes large clock networks efficiently. The ClockEdge tool automatically creates a transistor-level netlist for analysis, and then can simulate overnight to show you the fresh and aged results.

A new clock domain netlist is created from your existing files: Verilog, Lib, leaf cell definitions, constraints, SPEF. Simulation results are generated with full SPICE accuracy at your functional clock frequency for the fresh state. The clocks are then stressed as the second step of analysis. A third step is to use the aged clock domain netlist, run the full SPICE accurate simulation at the functional clock frequency and evaluate duty cycle distortion, insertion delay, rail to rail levels, and even clock slew rates. The difference between fresh and aged results tells the design team if they have a reliable design or not.

Delving into the first step, the fresh run analyzes the clock domain from the output of a PLL, all the way through to flip-flops or output pads. This clock domain can be quite large in size with millions of devices, and the transistor-level analysis results show us the delay and slew values.

The ClockEdge tool can run clock analysis for a fresh run on a block with 4.5 million gates, 517 million MOSFETs and 3.2 billion devices overnight, by using a distributed SPICE simulation approach. Your clock topology can be implemented as trees, grids and spines.

Step 2 is a stress run where specific transistors will be selected for aging, all depending on the circuit topology and if the clock is being parked (stuck at VDD or  VSS), or toggling. The stress run also depends upon temperature, voltage and duration per usage model.

The final analysis is Step 3, using the Aged devices. For the case of devices that had a parked clock value, then only one edge of clock will be affected during aging analysis, while devices with clock toggling will have both edges affected during aging analysis. So the Duty Cycle Delay (DCD) shape will depend on your circuit topology.

With ClockEdge a designer can perform what-if stress analysis, comparing the impact of a clock parked at 0, parked at 1, toggling, or even a combination of parked and toggling.

Summary

Clock aging is a new reliability concern, especially for IC designs at sub-10nm process nodes. With proper analysis, the effects of aging can be mitigated. Infinisim has the experience in analyzing the effects of clock aging. The ClockEdge tool from Infinisim is focused on giving designers accurate aging analysis of their clock networks, providing results quickly overnight. You get to see both DC and AC stress conditions for your aged clock domains.

Related Blogs

• Analyzing Clocks at 7nm and Smaller Nodes
• Methodology to Minimize the Impact of Duty Cycle Distortion in Clock Distribution Networks
• White Paper: A Closer Look at Aging on Clock Networks