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PCIe 5.0 Jumps to the Fore in 2019

PCIe 5.0 Jumps to the Fore in 2019
by Tom Simon on 03-06-2019 at 12:00 pm
Categories: IP, Synopsys

2019 will be a big year for PCIe. With the approval of version 0.9 of the Base Layer for PCIe 5.0, implementers have a solid foundation to begin working on designs. PCIe 4.0 was introduced in 2017, before that the previous PCIe 3.0 was introduced in 2010 – ages ago in this industry. In fact, 5.0 is so close on the heels of 4.0, many products… Read More

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How Good Are Your Clocks?

How Good Are Your Clocks?
by Paul McLellan on 04-29-2015 at 7:00 am
Categories: EDA, Empyrean

One of the trickiest tasks in designing a modern SoC is getting the clock tree(s) right. The two big reasons for this:

  • the clocks can consume 30% or more of the power of the whole chip, so minimizing the number of buffers inserted is critical to keeping power under control
  • the clock insertion delay and clock skew have a major impact on
… Read More
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Properly Handing Of Clock Tree Synthesis Specifications

Properly Handing Of Clock Tree Synthesis Specifications
by Randy Smith on 04-28-2013 at 1:00 pm
Categories: EDA, Empyrean

Given today’s design requirements with respect to low power, there is increasing focus on the contribution to total power made by a design’s clock trees. The design decisions made by the front-end team to achieve high performance without wasting power must be conveyed to back-end team. This hand-off must be accurate… Read More