DAC lunch seminar: Better IP Test with IEEE P1687

What: DAC lunch seminar (register here)
When: June 5, 2013, 11:30am – 1:30pm
Where: At DAC in lovely Austin, TX

Dr. Martin Keim of Mentor Graphics will present this overview of the new the IEEE P1687 standard, called IJTAG for ‘internal’ JTAG.

If you are involved in IC test*, you’ve probably heard about IJTAG. If you haven’t , it’s time to, because IJTAG defines a standard for embedded IP that vastly improves IP integration. It includes simple and portable descriptions supplied with the IP itself that create an environment for plug-and-play integration, access, test, and pattern reuse of embedded IP that doesn’t currently exist.

This seminar from Mentor Graphics covers the key aspects of IJTAG, including how it simplifies the design setup and test integration task at the die, stacked die, and system level. You will also learn about IP-level pattern reuse and IP access with IJTAG. Are you wondering what you need to do to migrate your existing 1149.1-based approach to P1687? Dr. Keim can tell you that too.

All the examples used in the seminar are from actual industrial use cases (from NXP and AMD). The presenter, Dr. Martin Keim, has the experience and technical chops to make this a very lunchtime seminar for everyone involved.

Register here.

If you’d like to study up on IJTAG before the seminar so you can ask the probing questions that make your fellow attendees jealous of your brains (in addition to your good looks), here’s a reasonable place to start — What’s The Difference Between Scan ATPG And IJTAG Pattern Retargeting?

*DFT managers, DFT engineers, DFT architects, DFT methodologist, IP-, Chip-, System-Design managers and engineers, IP-, Chip-, System-Test integrator, Failure analysis managers and engineers, system test managers, and system test engineers. Whew!