Atrenta will have a new look this year at DAC. I’m not quite sure what that means but we’ll all just have to go along and find out.
They have three users talking about their use of Atrenta’s tools. All 3 of these presentations are in the user-track poster session on Tuesday June 5th 12.30-1.30pm in room 105 (which is on the exhibit floor).
- Udupi Harisharan of Cisco will talk about SoC power budgeting and optimization using RTL-spreadsheet power estimation of ASICs.
- Cyril Vartanian of STMicroelectronics will talk about RTL restructuring with Atrenta Gensys.
- Ramesh Rejogopalan of Cisco will talk about Prevention of data loss in physical implementation of FIFOs and datapath synchronizers.
Atrenta’s CEO, Ajoy Bose, will discuss trade-offs and choices for emerging SoCs at the DAC management day. Tuesday June 5th from 2-4pm in room 309.
Atrenta Fellow Ravi Varadarajan will participate in a discussion on standards for the 3D world during the Si2 Roundup. Monday June 4th 3.15-4.30pm in room 301.
Of course Atrenta will be presenting their own tools in their booth, 2230. For details and to register go here.
Finally, come and celebrate with Atrenta and TSMC on Monday evening from 6-7pm in room 303 in the Moscone Center and on the outdoor terrace. The TSMC Soft-IP Alliance has already certified IP from ten providers as SpyGlass Clean. So grab a clean non-Spy glass and fill it with beer or wine.Share this post via: