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Open Letter from Sonics to Arteris

Open Letter from Sonics to Arteris
by Paul McLellan on 10-27-2013 at 2:00 pm

I don’t remember seeing an open letter from one EDA or IP company to another until today. Sonics have published an open letter to Charlie Janac, the CEO of Arteris. What seems to have happened is that Arteris have sold their assets to Qualcomm and the development team (which is based in France) and several AEs are already Qualcomm… Read More


The Biggest Private EDA Company

The Biggest Private EDA Company
by Paul McLellan on 10-21-2013 at 5:02 pm

I talked this morning with fellow Brit David Halliday. More importantly, he is CEO of Silvaco, which he thinks must be the biggest private EDA company in the world. He didn’t reveal their revenue numbers but they have around 250-300 people and are profitable so you can make your own estimate.

David became CEO when Ivan Pesic,… Read More


Analog & Mixed-Signal Design Lunch & Learn

Analog & Mixed-Signal Design Lunch & Learn
by Daniel Nenni on 10-20-2013 at 9:00 pm

I’m a big fan of lunch and learns, mainly because I’m a big fan of lunch but I also like to learn. I’m also a big fan of Tanner EDA which is why I helped organize this event. Face to face interaction amongst the fabless semiconductor ecosystem is critical to our success so stop on by and network, lunch is on me.

Take a look at the Brief HistoryRead More


GSA Memory+ Conference in Taiwan

GSA Memory+ Conference in Taiwan
by Paul McLellan on 10-18-2013 at 3:02 pm

The GSA Memory+ conference Taiwan will take place on (Halloween!) October 31, 2013 at the Regent Taipei, Taiwan. The main theme of this year is highlighting Memory—the Critical Enabler for Prominent and Emerging Applications in System Logic Solutions.

GSA Memory+ Conference is the global industry event dedicated to all memory… Read More


Semiconductor IP Library QA Just Got Easier

Semiconductor IP Library QA Just Got Easier
by Daniel Payne on 10-17-2013 at 12:05 pm

Imagine that you’re working in a CAD group and just received a new library of a few hundred IP blocks and you needed to know if these blocks conform to your design and quality standards. There are many questions about library and IP quality:

  • Are all of the views consistent (layout, schematic, HDL, test, timing, SPICE)?
  • Are there
Read More

GSA hosting “Interface IP: Winners, Losers in 2013” from IPnest

GSA hosting “Interface IP: Winners, Losers in 2013” from IPnest
by Eric Esteve on 10-17-2013 at 5:32 am

The GSA IP Working Group will meet today in San Jose, and the Group has asked IPnest building a presentation dedicated to Interface IP. The timing was perfect, as I have just completed the “Interface IP Survey” version 5, and I was able to use fresh market data. The IP working group will discover the IP vendor ranking, protocol by protocol,… Read More


Enter the Warrior

Enter the Warrior
by Paul McLellan on 10-14-2013 at 11:57 am

Since Imagination’s acquisition of MIPS at the end of last year, the MIPS product line has been given a new lease of life. There are two things driving this. The first is simply that with its new home, the MIPS architecture has a solid future whereas before it was uncertain. Secondly, Imagination moved their own general purpose… Read More


Driving Innovation in Image Sensors and High Speed AMS Design!

Driving Innovation in Image Sensors and High Speed AMS Design!
by Daniel Nenni on 10-13-2013 at 7:00 am


This is a live Silicon Valley event and yes there is such a thing as a free lunch. This is the first in a series of live SemiWiki collaborative events. I strongly believe that, especially in the age of social media, real world experience is key to the collaboration required to be successful in modern day semiconductor design. This is… Read More


What Can Accelerate 3D Semiconductor Manufacturing?

What Can Accelerate 3D Semiconductor Manufacturing?
by Pawan Fangaria on 10-12-2013 at 9:30 am

In the beginning of this decade there was a lot of buzz around 3D chip manufacturing. Many EDA tools were developed to facilitate semiconductor designs in 3D space. Naturally, we are moving to the edge on 2D without much room to further squeeze transistors and interconnect. However, lately I haven’t heard much about 3D products.… Read More


High resolution Analog CMOS IC Design

High resolution Analog CMOS IC Design
by Daniel Payne on 10-04-2013 at 5:02 pm

My background includes transistor-level IC design, so I take delight in talking with engineers like Dr. Lanny Lewyn that are still practicing the art and science of analog IC design. Dr. Lewynis a Life Senior Member of the IEEE and has a consulting business. If you live in Santa Clara, then consider attending a live seminar on OctoberRead More