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Intel Invests in the Fabless Ecosystem!

Intel Invests in the Fabless Ecosystem!
by Daniel Nenni on 06-22-2014 at 11:00 am

During my illustrious career one of the most useful axioms that I use just about everyday day is: “Understand what people say but also understand why they are saying it.” This certainly applies to press releases so let’s take a look at what Intel unleashed during #51DAC (in alphabetical order):

ANSYS And Intel Collaborate
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ARC EM DSP supports Always-on Devices

ARC EM DSP supports Always-on Devices
by Eric Esteve on 06-22-2014 at 3:01 am

The ARC EM family is the low-power, embedded and low footprint processor part of the larger ARC processor. To target the ultra low-power markets like wearable and IoT, Synopsys has added DSP capabilities to EM5D and EM7D. To be specific, these cores are optimized for ultra low-power control and DSP, thanks to:

  • Energy-efficient
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IP Accelerated (Bye Bye EDA 360)

IP Accelerated (Bye Bye EDA 360)
by Eric Esteve on 06-12-2014 at 9:53 am

Synopsys has been extremely active, during the last 10 years, not only launching new IP products every year, but also running an ambitious acquisition strategy, with no less than 8 acquisitions. Cascade acquisition bring PCI Express (controller only), when Accelerant bring SerDes (the earth of any PHY IP). The MIPS/Chipidea… Read More


Synopsys Galaxy Platform & Lynx Design System supports FD-SOI

Synopsys Galaxy Platform & Lynx Design System supports FD-SOI
by Eric Esteve on 06-05-2014 at 11:36 am

This is a new brick that Synopsys brings to build FD-SOI credibility. We have talked at Semiwiki about FD-SOI technology developed by the LETI and STM, and recently endorsed by Samsung Foundry, offering a more than credible second source to STM. And we have said that the FD-SOI introduction will need to be supported by EDA and IP vendors… Read More


Non-separation of power and performance

Non-separation of power and performance
by Don Dingee on 06-04-2014 at 2:00 pm

How much power does a system consume? The simplistic path to power estimation for a system used to be tossing a few metrics – standby, typical, worst case, with figures pulled from a datasheet, simulation, or physical measurement – into a spreadsheet. After filling the remaining holes with SWAG (scientific wild-ass guesses), … Read More


IoT Breakfast Panel at DAC

IoT Breakfast Panel at DAC
by Daniel Payne on 06-03-2014 at 7:21 pm

Tuesday morning at DAC I enjoyed a free breakfast courtesy of Synopsysand GLOBALFOUNDRIESwhere I learned more about the emerging market of IoT, and what it means to semiconductor, EDA and IP vendors. Panelists included: Semico Research, HP, Synopsys, GLOBALFOUNDRIES and Broadcom. … Read More


Understanding QoR in FPGA synthesis

Understanding QoR in FPGA synthesis
by Don Dingee on 05-28-2014 at 8:00 am

We’ve all heard this claim: “Our FPGA synthesis tool produces better quality of results (QoR).” If you’re just hoping for a tool to do that automagically, you’re probably doing it wrong. Getting better QoR depends on understanding what an FPGA synthesis tool is capable of, and how to leverage what it tells you.… Read More


Synopsys @ #51DAC Must See!

Synopsys @ #51DAC Must See!
by Daniel Nenni on 05-14-2014 at 11:00 am

Accelerating Innovation—that has been at the heart of Synopsys’ commitment to its customers for more than 25 years. As a leader in EDA and semiconductor IP, Synopsys’ software, IP and services help engineers address their design, verification, system and manufacturing challenges and accelerate their innovations. Since 1986,… Read More


Selecting the Right Standard Cell & Memory for 28HPM DSP core: real case with CEVA XC4210

Selecting the Right Standard Cell & Memory for 28HPM DSP core: real case with CEVA XC4210
by Eric Esteve on 05-09-2014 at 11:14 am

Listening to a webinar at your desk, in front of a PC screen will never replace a live presentation, but the lesson learned to time spent ratio can be incredibly higher than when traveling to a conference to listen several presentation. If you are interested by the approach taken by a complex DSP design team to overcome the various … Read More