Banner Electrical Verification The invisible bottleneck in IC design updated 1
WP_Term Object
(
    [term_id] => 386
    [name] => Semiconductor Services
    [slug] => semiconductor-services
    [term_group] => 0
    [term_taxonomy_id] => 386
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 1155
    [filter] => raw
    [cat_ID] => 386
    [category_count] => 1155
    [category_description] => 
    [cat_name] => Semiconductor Services
    [category_nicename] => semiconductor-services
    [category_parent] => 0
    [is_post] => 
)

1.2 Terabit/s C2C Interface? Only with Interlaken!

1.2 Terabit/s C2C Interface? Only with Interlaken!
by Eric Esteve on 04-24-2017 at 7:00 am

If you are familiar with high bandwidth networking applications, you probably know this chip-to-chip (C2C) interface protocol. Interlaken architecture, fully flexible, configurable and scalable, is also an elegant answer to the need for very high bandwidth C2C communication. Interlaken is elegant because the protocol … Read More


IP Vendors: Call for Contribution to the Design IP Report!

IP Vendors: Call for Contribution to the Design IP Report!
by Eric Esteve on 04-13-2017 at 12:00 pm

The EDA & IP industry enjoys high growth for the Design IP segment, but a detailed analysis tool is missing. IPnest will address this need in 2017, expecting the IP vendors’ contribution! If we consider the results posted last March by the ESD Alliance, the EDA (and IP) industry is doing extremely well, as the global revenue has… Read More


Apple Going (IP) Vertical with no Imagination!

Apple Going (IP) Vertical with no Imagination!
by Eric Esteve on 04-03-2017 at 12:00 pm

What conclusion could we derive from the recent (April 3) PR from Imagination where we learn that the company “has been notified by Apple Inc. (“Apple”), its largest customer, that Apple is of a view that it will no longer use the Group’s intellectual property in its new products in 15 months to two years time, and as such will not be … Read More


Seven Reasons to Use FPGA Prototyping for ASIC Designs

Seven Reasons to Use FPGA Prototyping for ASIC Designs
by Daniel Payne on 03-28-2017 at 12:00 pm

Using an FPGA to prototype your next hardware design is a familiar concept, extending all the way back to the time that the first FPGAs were being produced by Xilinx and Altera. There are multiple competitors in the marketplace for FPGA prototyping, so I wanted to discern more about what the German-based company PRO DESIGN had to … Read More


eFabless Design Challenge Results!

eFabless Design Challenge Results!
by Daniel Nenni on 03-28-2017 at 7:00 am

Will community engineering work for semiconductors? Will anyone show up? Well, the efabless design challenge is complete and the results are both interesting and encouraging, absolutely!

Efabless completed its low power voltage reference IP design challenge on Monday, March 13. This was a very interesting event that we followed… Read More


China to become largest semiconductor producer

China to become largest semiconductor producer
by Bill Jewell on 03-24-2017 at 12:00 pm

China has long been the largest market for semiconductors, accounting for over 50% of the global market for the last five years. China is now on track to become the largest semiconductor manufacturer in the next few years. The chart below shows China’s integrated circuit (IC) industry from 2010 to 2016, according to the China Semiconductor… Read More


Samsung Should Just Buy eSilicon Already!

Samsung Should Just Buy eSilicon Already!
by Daniel Nenni on 03-22-2017 at 12:00 pm

As you all know I’m a big fan of the ASIC business dating back to the start of the fabless semiconductor transformation where anybody could send a design spec to an ASIC company and get a chip back. The ASIC business model also started the smart phone revolution when Samsung built the first Apple SoCs for the iPhones and iPads.

Today … Read More


Succeeding with 56G SerDes, HBM2, 2.5D and FinFET

Succeeding with 56G SerDes, HBM2, 2.5D and FinFET
by Daniel Nenni on 03-17-2017 at 4:00 pm

eSilicon presented their advanced ASIC design capabilities at a seminar last Wednesday evening. This event was closed to the press, bloggers and analysts, but I managed to get some details from a friend who attended. The event title was: “Advanced ASICs for the Cloud-Computing Era: Succeeding with 56G SerDes, HBM2, 2.5D and FinFETRead More


Six Reasons to Consider Using FPGA Prototyping for ASIC Designs

Six Reasons to Consider Using FPGA Prototyping for ASIC Designs
by Daniel Payne on 03-15-2017 at 12:00 pm

There’s no doubt that programmable logic in FPGAs have transformed our electronics industry for the better. If you do ASIC designs then there’s always the pressure of getting first silicon correct, with no functional or timing bugs, because bugs will cause expensive re-spins and delay time to market. ASIC designers… Read More


Lu Dai: Incoming Accellera Chair

Lu Dai: Incoming Accellera Chair
by Bernard Murphy on 03-11-2017 at 7:00 am

One of the fun things about what I do is getting to meet some of the movers and shakers in the industry. You might not think of Accellera as a spot to find movers and shakers, but when you consider the impact they have had on what we do (OVL, SystemVerilog, UVM, UPF, SystemC, IP-XACT and others), design today would be unrecognizable without… Read More