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Samsung and TSMC have both made recent disclosures about their 5nm process and I though it would be a good time to look at what we know about them and compare the two processes.
A lot of what has been announced about 5nm is in comparison to 7nm so we will first review 7nm.
7nm
Figure 1 compares Samsung’s 7LPP process to TSMC’s 7FF and 7FFP… Read More
The use of hard masks instead of photoresist for the Extension implant is an effective way to optimize the amount of dopant that is retained along the fin sidewalls for those fins that border along photoresist edges (as discussed in Part 1 of this series).
However, hard masks do nothing to address the dominant problem driving steeper… Read More
The 3D character of FinFET transistor structures pose a range of unique fabrication problems that can make it challenging to get these devices to yield. This is especially true for the all-important Extension implant that is put in place just prior to the nitride spacer formation.
The Extension implant is a central component of… Read More
The semiconductor equipment market grew 37.3% in 2017 on the heels of capex spend by memory companies in order to increase bit capacity and move to more sophisticated products with smaller nanometer dimensions. Unfortunately these companies overspent resulting in excessive oversupply of memory chips. As memory prices started… Read More
It was the best of times (for stocks)
It was the worst of times (for memory chips)
The disconnect between stock & chip prices
The Venn Diagram of Stocks and Chips
Having been involved with semiconductor and tech stocks for a long time there has always been a loose correlation between the fortunes of the industry and the fortunes… Read More
At the SPIE Advanced Lithography Conference Imec presented several papers on EUV and Veeco presented about etching for EUV masks. I had the opportunity to see the presentations and speak with some of the authors. In this article I will summarize the key issues around EUV based on this research.
EUV is ramping up into high volume 7nm… Read More
The Dutch financial newspaper Financieele Dagblad (FD) reported on the past theft of ASML technology after doing some investigative digging. It now appears that a number of Chinese nationals and ASML employees, in ASML’s Santa Clara office stole key technology back in 2015. Though ASML talked about it at the time, little… Read More
Like many others, we have often wondered why the PMOS fins on advanced microprocessors from Intel are narrower than the NMOS fins (6nm versus 8nm). This unusual dimensional difference first occurred at the 14nm node and it coincided with the introduction of Solid State Doping (SSD) of the fins at this node.
We have concluded that… Read More
An informal “Fireside Chat” like no other featuring Jim Hogan, managing partner of Vista Ventures, LLC., and Paul Cunningham, Cadence’s corporate vice president and general manager of the system verification group, is in the works for Wednesday, April 10.
Hosted by the ESD Alliance, a SEMI Strategic Association Partner, at … Read More
I plan to attend to the GSA European Forum in Munich (April 15-16), so I first looked at the event description and at the impressive speakers list. In such event, the goal is at 50% to listen, and 50% to network with the speakers and the other attendant. The center of gravity is clearly semiconductor, but the event involved speakers … Read More
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