At the Samsung theatre (cutely named the Samsung Open Collaboration (SoC) theater) I watched a presentation by KK Lin on using DFM to bring up their 14nm and 10nm processes. And yes, they are real. Here is a picture I took of a 14nm wafer and a 10nm wafer. Samsung announced that they would ramp 10n to volume production by the end of next… Read More
A Closer Look at Fab Closures Around the World
Electronics is unusually an evergreen industry where companies make profit, yet end-product prices go down significantly after a brief period of price skimming. A product phases out quite fast (in case of smartphones every 1.5 to 2 years), but still yields big bucks for successful companies in its value-chain. How does this happen?… Read More
EUV: the view from imec
I’m at the 2015 imec technology forum (ITF) in Brussels the next few days. One of the presentations today was by Peter Wennink, the CEO of ASML. The thing that most interested me in his presentation is what the status of EUV is today. ASML is the only company developing EUV steppers so what they think is important. On the other … Read More
GlobalFoundries IBM Deal to Close July 1st!
Probably one of the most awaited semiconductor events is coming next week if the Poughkeepsie Journal is correct, which from what I’m told by my Albany friends, they are. The official announcement was made last October using the slide deck which can be found HERE. It was originally thought that the approval process would take a year… Read More
Can FD-SOI Change the Rule of Game?
It appears so. Why there is so much rush towards FD-SOI in recent days? Before talking about the game, let me reflect a bit on the FD-SOI technology first. The FD-SOI at 28nm claims to be the most power-efficient and lesser cost technology compared to any other technology available at that node. There are many other advantages from… Read More
Further Delays for Intel 10nm?
Intel’s 10nm may be reliving the 14nm elongated delay issue-
Schedules & tool delivery may be pushed even deeper into 2016-
Meanwhile Samsung & TSMC press on-
Could Intel be embarrassed?
… Read More
Extending EUV Lithography
I have previously written about SPIE day 1 and 2 so I want to wrap up my coverage with some impressions from days 3 and 4. My single biggest take away from the conference is that EUV has made tremendous progress in the last 12 months. Last year the mood of the conference was in my opinion pessimistic with respect to EUV, this year the mood… Read More
eSilicon@Samsung: ASIC Design, IP Enablement, and Cloud Platform
Earlier this week at DAC, Javier DeLaCruz of eSilicon presented at the Samsung booth. They presented an introduction to what eSilicon does. However, since what they do has changed over the years it is useful to recap. If you know about eSilicon then you probably think of them as a fabless ASIC company. The old ASIC model back in the … Read More
DAC Keynote: Moore’s Law Isn’t Dead
There were two keynotes at DAC this morning. I think the official designation of the first one was a “visionary talk” and the main difference was that it was only 15 minutes long. Vivek Singh, an Intel fellow, talked about Moore’s Law at 50: No End in Sight.
He started with a graph showing transistor speed versus… Read More
TSMC Shows 10nm Wafer!
If you really want to know why I write about TSMC it is all about ego, my massive ego, absolutely. Blogs about TSMC and the foundries have always driven the most traffic and they most likely always will. Semiconductor IP is second, Semiconductor Design is third, and I don’t think that is going to change anytime soon:
SemiWiki BI: Daniel… Read More
AI RTL Generation versus AI RTL Verification