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Webinar: Build Your Next HBM2/2E Chip with SiFive

Webinar: Build Your Next HBM2/2E Chip with SiFive
by Mike Gianfagna on 05-04-2020 at 10:00 am

Screen Shot 2020 05 03 at 12.09.58 PM

I have been watching the trend for quite some time now that many advanced FinFET designs today are actually 2.5D systems in package. All of these 2.5D silicon interposer-based designs have high-bandwidth memory (HBM) stacks on board.  Often there are multiple memory stacks in both 4-high and 8-high configurations. If you follow… Read More


Talking Sense With Moortec…Are You Listening?!

Talking Sense With Moortec…Are You Listening?!
by Tim Penhale-Jones on 05-04-2020 at 10:00 am

Ear no evil

It almost doesn’t matter what your job may be, whether in the public sector or a private company, or how technical or how dangerous, many of life’s adages and sayings can be interpreted to have some direct meaning for all of us.

Over the years in our personal lives, we have been constantly advised that prevention is better than cure…certainly… Read More


Webinar: Real-time In-Chip Monitoring to Boost multi-core AI, ML, DL Systems

Webinar: Real-time In-Chip Monitoring to Boost multi-core AI, ML, DL Systems
by Daniel Payne on 04-28-2020 at 10:00 am

hot spots

During the COVID-19 pandemic I’m using Zoom and attending more webinars to keep updated on semiconductor industry trends, and one huge trend is the importance of AI applied to SoCs. Using more cores to handle ML and DL makes sense, but then how do you keep the chips within their power and reliability limits while at the same … Read More


AI, Safety and Low Power, Compounding Complexity

AI, Safety and Low Power, Compounding Complexity
by Bernard Murphy on 04-28-2020 at 6:00 am

Hoc in a low-power ASIL-D design

The nexus of complexity in SoC design these days has to be in automotive ADAS devices. Arteris IP highlighted this in the Linley Processor Conference recently where they talked about an ADAS chip that Toshiba had built. This has multiple vision and AI accelerators, both DSP and DNN-based. It is clearly aiming for ISO 26262 ASIL D … Read More


Synopsys – Turbocharging the TCAM Portfolio with eSilicon

Synopsys – Turbocharging the TCAM Portfolio with eSilicon
by Mike Gianfagna on 04-27-2020 at 10:00 am

Screen Shot 2020 04 18 at 2.21.03 PM

About 90 days ago, Synopsys completed the acquisition of certain IP assets from eSilicon. The remaining entirety of eSilicon was acquired by Inphi Corporation. I was the VP of marketing at eSilicon during that acquisition so it’s very interesting to me to find out how things are going with those certain IP assets.  I got an opportunity… Read More


SiFive’s Approach to Embedding Intelligence Everywhere

SiFive’s Approach to Embedding Intelligence Everywhere
by Tom Simon on 04-27-2020 at 6:00 am

SiFive Embedding Intelligence

Before the advent of RISC-V, designers looking for embedded processors were effectively limited to a handful of proprietary processors using ISAs from decades ago. While the major ISAs are being updated and enhanced, they also are facing limitations from many decisions made over many years.  RISC-V was conceived with a clean… Read More


Key Applications for Chip Monitoring

Key Applications for Chip Monitoring
by Daniel Nenni on 04-24-2020 at 2:00 pm

Richard McPartland

One of the side benefits of working with SemiWiki is that you get to meet a broad range of people and in the semiconductor industry that means a broad range of very smart people, absolutely. Recently I had the pleasure to meet Richard McPartland of Moortec. Richard and I started in the semiconductor industry at the same time but from… Read More


Using ML Acceleration Hardware for Improved DSP Performance

Using ML Acceleration Hardware for Improved DSP Performance
by Tom Simon on 04-24-2020 at 6:00 am

nnMAX Flex Logix Tile

Some amazing hardware is being designed to accelerate AI/ML, most of which features large numbers of MAC units. Given that MAC units are like the lego blocks of digital math, they are also useful for a number of other applications. System designers are waking up to the idea of repurposing AI accelerators for DSP functions such as … Read More


Wi-Fi Bulks Up

Wi-Fi Bulks Up
by Bernard Murphy on 04-23-2020 at 6:00 am

Wi Fi

Wireless discussion these days seems to be dominated by 5G, but that’s not the only standard that’s attracting attention. The FCC just circulated draft rules to dramatically expand bandwidth available to Wi-Fi in the new Wi-Fi 6e standard.

Is this a tragic plea for attention from a once-important standard, now eclipsed by its … Read More


Accelerating Edge Inference with Flex Logix’s InferX X1

Accelerating Edge Inference with Flex Logix’s InferX X1
by Mike Gianfagna on 04-22-2020 at 10:00 am

Screen Shot 2020 04 11 at 6.29.49 PM

For a long time, memories were the primary technology driver for process development. If you built memories, you got access to cutting-edge process information. If you built other products, this could give you a competitive edge. In many cases, FPGAs are replacing memories as the driver for advanced processes. The technology… Read More