Time-sensitive networking for aerospace and defense applications is receiving new attention as a new crop of standards and profiles approaches formal release, anticipated before the end of 2024. CAST, partnering with Fraunhofer IPMS, has developed a suite of configurable IP for time-sensitive networking (TSN) applications,… Read More
Semiconductor Intellectual Property
Analog Bits Continues to Dominate Mixed Signal IP at the TSMC Technology Symposium
The recent TSMC Technology Symposium in the Bay Area showcased the company’s leadership in areas such as solution platforms, advanced and specialty technologies, 3D enablement and manufacturing excellence. As always, the TSMC ecosystem was an important part of the story as well and that topic is the subject of this post. Analog… Read More
Ceva Accelerates IoT and Smart Edge AI with a New Wireless Platform IP Family
Ceva is a very focused company. In its words, the leader in innovative silicon and software IP solutions that enable smart edge products to connect, sense, and infer data more reliably and efficiently. You can see some of its accomplishments here. The company has been licensing IP for more than twenty years with more than 17 billion… Read More
Alphawave Semi Bridges from Theory to Reality in Chiplet-Based AI
GenAI, the most talked-about manifestation of AI these days, imposes two tough constraints on a hardware platform. First, it demands massive memory to serve large language model with billions of parameters. Feasible in principle for a processor plus big DRAM off-chip and perhaps for some inference applications but too slow … Read More
Semi Market Decreased by 8% in 2023… When Design IP Sales Grew by 6%!
Design IP revenues had achieved $7.04B in 2023, with disparity between license, growing by 14% and royalty decreasing by 6%, and main categories. Processor (CPU, DSP, GPU & ISP) slightly growing by 3.4% when Physical (SRAM Memory Compiler, Flash Memory Compiler, Library and I/O, AMS, Wireless Interface) slightly decreasing… Read More
Semidynamics Shakes Up Embedded World 2024 with All-In-One AI IP to Power Nextgen AI Chips
Semidynamics takes a non-traditional approach to design enablement. Not long ago, the company’s Founder and CEO, Roger Espasa unveiled extreme customization at the RISC-V Summit. That announcement focused on a RISC-V Tensor Unit designed for ultra-fast AI solutions. Recently, at Embedded World 2024 the company took this … Read More
Silicon Catalyst partners with Arm to launch the Arm Flexible Access for Startups Contest!
Winner and Runner-up to receive the contest’s largest ever technology credit for production tape-outs.
This is an example of why I enjoy working with Silicon Catalyst. They collaborate with our partners and do some really impressive things, all for the greater good of the semiconductor industry, absolutely. If you are not currently… Read More
Synopsys Design IP for Modern SoCs and Multi-Die Systems
Semiconductor intellectual property (IP) plays a critical role in modern system-on-chip (SoC) designs. That’s not surprising given that modern SoCs are highly complex designs that leverage already proven building blocks such as processors, interfaces, foundational IP, on-chip bus fabrics, security IP, and others. This… Read More
Enhancing the RISC-V Ecosystem with S2C Prototyping Solution
RISC-V’s popularity stems from its open-source framework, enabling customization, scalability, and mitigating vendor lock-in. Supported by a robust community, its cost-effectiveness and global adoption make it attractive for hardware innovation across industries.
Despite its popularity, evolving RISC-V architectures… Read More
Arteris Frames Network-On-Chip Topologies in the Car
On the heels of Arm’s 2024 automotive update, Arteris and Arm announced an update to their partnership. This has been extended to cover the latest AMBA5 protocol for coherent operation (CHI-E) in addition to already supported options such as CHI-B, ACE and others. There are a couple of noteworthy points here. First, Arm’s new Automotive… Read More
TSMC N3 Process Technology Wiki