SILVACO 051525 Webinar 800x100 v2
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IP

Semiconductor Intellectual Property

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Interconnect Optimization of an SoC Architecture

Interconnect Optimization of an SoC Architecture
by Daniel Payne on 03-20-2013 at 11:41 am
Categories: Arm, EDA, IP

My last chip design at Intel was a GPU called the 82786and the architects of the chip wrote a virtual prototype using the MAINSAIL language. By using a virtual prototype they were able to:

  • Simulate bus traffic, video display and video RAM
  • Determine throughput
  • Measure latency
  • Verify that bus priorities were working
  • Optimize the
… Read More
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Create Beyond the NoC Solutions!

Create Beyond the NoC Solutions!
by Eric Esteve on 03-18-2013 at 9:09 am
Categories: Arteris, IP

The Network On Chip (NoC) concept is recent, about 10 years old, and the first implementation of commercially available NoC IP has happened in 2006. Should we drop the concept so quickly after it has been introduced? In fact, I don’t think so… But we could brain storm and imagine the new functions that could be implemented within or… Read More

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ARM Cortex SoC Prototyping Platform for Industrial Applications

ARM Cortex SoC Prototyping Platform for Industrial Applications
by Daniel Payne on 03-14-2013 at 1:00 pm
Categories: Aldec, Arm, EDA

If your next SoC uses an ARM Cortex-A9 and has an industrial application, then you can save much design and debug time by using a prototyping platform. The price to prototype is quite affordable, and the methodology has a short learning curve. Bill Tomasan Aldec Research Engineer conducted a webinar today on: ARM Cortex SoC Prototyping… Read More

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Will next generation Mobile Devices support PCI Express? M-PCIe is coming fast!

Will next generation Mobile Devices support PCI Express? M-PCIe is coming fast!
by Eric Esteve on 03-14-2013 at 6:22 am
Categories: Cadence, IP

Those who have read the numerous articles I have written about MIPI, or PCIe, or the fusion of both named “Mobile Express” know my position: the question is not “Will Mobile devices support PCI Express?” but “When will we see Mobile devices integrating Mobile Express?” I was not really surprised by the Press Release that Cadence … Read More

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Cadence To Acquire Tensilica

Cadence To Acquire Tensilica
by Paul McLellan on 03-11-2013 at 5:54 pm
Categories: Cadence, IP

You have probably already seen the news: Cadence is acquiring Tensilica for $380M. Cadence has been relatively late to the IP party compared to Synopsys. In contrast, Mentor was early, got into the IP business before it was really profitable and ended up shutting down the business.

Tensilica is quite sizable. It has over 200 licensees,… Read More

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Qualcomm and Intel Dynasty Scenario at 14nm

Qualcomm and Intel Dynasty Scenario at 14nm
by Ed McKernan on 03-08-2013 at 1:00 pm
Categories: Arm, Foundries, Intel Foundry, TSMC

At a different time, but certainly within the past 12 months, Paul Otellini was asked if Intel would be a Foundry for Qualcomm. His reply was that it did not leave a good taste in his mouth. Nevertheless it was not rejected and the door that remained open just a crack is likely to swing open for Qualcomm, the premier mobile silicon supplier… Read More

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Multiprotocol 10G-KR and PCIe Gen-3 PHY IP will support big data and smartphone explosion

Multiprotocol 10G-KR and PCIe Gen-3 PHY IP will support big data and smartphone explosion
by Eric Esteve on 03-07-2013 at 7:47 am
Categories: IP, Synopsys

We have frequently said in Semiwiki how crucial is it for the SC industry to benefit from high quality PHY IP… even if, from a pure business point of view (MBA minded), PHY IP business does not look so attractive. In fact, to be able to design on-the-edge SerDes and PLL (the two key pieces), you need to build and maintain a highly skilled… Read More

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OTP based Analog Trimming and Calibration

OTP based Analog Trimming and Calibration
by Eric Esteve on 03-01-2013 at 10:16 am
Categories: IP, Sidense

Embedded NVM technology based functions can be implemented in large SoC designed in advanced technology nodes down to 28nm, as there is no requirement for extra mask levels, like when integrating Nand Flash, negatively impacting the final cost. And it is also possible to integrate One Time Programmable (OTP) to store trim and … Read More

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MUST: DSP ready solution for tomorrow smartphone based on CEVA-XC 4000

MUST: DSP ready solution for tomorrow smartphone based on CEVA-XC 4000
by Eric Esteve on 02-24-2013 at 5:13 am
Categories: Ceva, IP

Like Guiness dark beer, competition is good for you! I mean good for end user, as it pushes DSP IP supplier to provide ever better solution. I am not talking about me-to type of competition, like that we have seen in the past with IBM trying to displace TI at Nokia, by offering a LEAD (DSP IP core from TI used in every NOKIA wireless phone… Read More

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Modeling TSV, IBIS-AMI and SERDES with HSPICE

Modeling TSV, IBIS-AMI and SERDES with HSPICE
by Daniel Payne on 02-21-2013 at 8:10 pm
Categories: EDA, IP, Synopsys

The HSPICE circuit simulator has been around for decades and is widely used by IC designers worldwide, so I watched the HSPICE SIG by video today and summarize what happened. Engineers from Micron, Altera and AMD presented on how they are using HSPICE to model TSVs, IBiS-AMI models and SERDES, respectively.… Read More