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RISC-V opens for business with SiFive Freedom

RISC-V opens for business with SiFive Freedom
by Don Dingee on 07-11-2016 at 4:00 pm

When we talk about open source, free usually comes in the context of “freedom”, not as in “free beer”, and open IP often serves as a base layer of value add for commercialization. The creators of the RISC-V instruction set, now working at startup SiFive, have released specifications for their aptly-named Freedom processor IP cores… Read More


How to Bring Coherency to the World of Cache Memory

How to Bring Coherency to the World of Cache Memory
by Tom Simon on 07-11-2016 at 12:00 pm

As the size and complexity of System On Chip design has rapidly expanded in recent years, the need to use cache memory to improve throughput and reduce power has increased as well. Originally, cache memory was used to prevent what was then a single processor from making expensive off chip access for program or data memory. With the… Read More


Artificial Intelligence is Everything!

Artificial Intelligence is Everything!
by Daniel Nenni on 07-08-2016 at 7:00 am

My first brush with AI was a LISP class for my undergraduate degree. LISP, originated from MIT in 1958, was the language of choice for AI research and spawned a new class of computer hardware called LISP Machines in the 1980s. My first personal experience with AI was the HAL 9000 system from the 2001 Stanley Kubrik movie Space Odyssey.… Read More


STT-MRAM – Coming soon to an SoC near you

STT-MRAM – Coming soon to an SoC near you
by Tom Dillinger on 07-05-2016 at 4:00 pm

An increasing percentage of SoC die area is being allocated to memory arrays, as applications require more data/instruction storage and boot firmware. Indeed, foundries invest considerable R&D resources into optimizing their array technology IP offerings, often with more aggressive device features than used for other… Read More


21 months lining up OPNFV-on-ARM for telecom

21 months lining up OPNFV-on-ARM for telecom
by Don Dingee on 07-01-2016 at 4:00 pm

Telecom infrastructure is one area where X86 architecture hasn’t dominated historically. Infrastructure gear is spread across MIPS, Power, and SPARC architectures, with some X86, and a relative newcomer: ARM, already claiming 15% share. That’s a stunning figure considering only a bit less than 5 years ago… Read More


Synopsys Launch EV6x Vision Processor… Challenging the Competition!

Synopsys Launch EV6x Vision Processor… Challenging the Competition!
by Eric Esteve on 06-30-2016 at 4:00 pm

When Synopsys bought Virage Logic in 2010, ARC processor IP was in the basket, but at that time ARC processor core was not the most powerful on the market, and by far. The launch of EV6x vision processor sounds like Synopsys has moved ARC processor core by several orders of magnitude in term of processing power. EV6x deliver up to 100X… Read More


Software Security is Necessary but NOT Sufficient

Software Security is Necessary but NOT Sufficient
by Dr. Jason Oberg on 06-30-2016 at 12:00 pm

As the silicon designs inside the connected devices of the Internet of Things transition from specifications to tapeouts, electronics companies have come to the stark realization that software security is simply not adequate. Securing silicon is now a required, not optional, part of RTL design processes.… Read More


From Zero to IoT Prototype in One Month

From Zero to IoT Prototype in One Month
by Bernard Murphy on 06-30-2016 at 7:00 am

The best things in life may not always be free, but they don’t have to be incredibly difficult to get to. A challenge for IoT designers has been that their bubbling excitement over the potential of their new gizmo is quickly tempered by the complexities of actually building the hardware. Not exactly what they have come to expect in … Read More


HBM controller IP holds the key to bandwidth

HBM controller IP holds the key to bandwidth
by Don Dingee on 06-29-2016 at 4:00 pm

We were waiting to see what a different roster including SK Hynix and Synopsys would have to say on HBM in the latest Open Silicon webinar. This event focused on HBM bandwidth issues; a packaging session on 2.5D interposers was promised for a future webinar.… Read More