The speed and power penalties for accessing system RAM affect everything from artificial intelligence platforms to IoT sensor nodes. There is a huge power and performance overhead when the various IP blocks in an SOC need to go to DRAM. Memory caches have become essential to SOC design to reduce these adverse effects. However, … Read More
Semiconductor Intellectual Property
ARM Server Update (NFV)
There has been a lot of buzz in the industry over the last several years about ARM Holdings’ and its partners’ plans to go after the datacenter market with a particular focus on servers. Companies like Advanced Micro Devices, Applied Micro Circuits Corp. (AppliedMicro), Cavium, and Qualcomm, are now in various stages of product… Read More
Why NXP is Moving to FD-SOI (Part II)
At NXP, we’re very excited about the prospects for our new i.MX 7 and 8 series of applications processors, which we’re manufacturing on 28nm FD-SOI. As noted in part I of this article series, the new i.MX 7 series, which leverages the 32-bit ARM v7-A core, is targeting the general embedded, e-reader, medical, wearable… Read More
Sonics opens new strategy for SoC energy processing
Back in February when we shared the Sonics philosophy on the ICE-Grain Power Architecture for hardware-based SoC power management, I speculated we’d know more by DAC 2016. Sonics is hitting the road with a new live seminar coming to Silicon Valley this month and Austin during DAC – and the news is big.… Read More
Why is NXP Moving to FD-SOI?
The latest generations of power efficient and full-featured applications processors in NXP’s very successful and broadly deployed i.MX platform are being manufactured on 28nm FD-SOI. The new i.MX 7 series leverages the 32-bit ARM v7-A core, targeting the general embedded, e-reader, medical, wearable and IoT markets, where… Read More
Qualcomm’s New Smartphone Chips Go Straight At MediaTek
Last Thursday at Qualcomm’s Financial Analyst Day the company made a slew of chip announcements ranging from the industry’s 1 Gbps wireless LTE modem to a custom designed smartwatch SoC and platform called “Snapdragon Wear 2100 SoC”. In between those, Qualcomm also announced a few very overlooked … Read More
Are Standard Cell Libs, Memories and Mixed-signal IP Availabe at 7nm FF?
More than 500 designers (562) have responded to a survey made in 2015 by Synopsys. Answering to the question “What is the fastest clock speed of your design?” 56% have mentioned a clock higher than 500 MHz (and still 40% higher than 1 GHz). If you compare with the results obtained 10 years ago, the largest proportion of answers was for… Read More
Is Tesla Making Their Own CPUs?
One of the benefits of administering a leading semiconductor design enablement portal is that I get to see the traffic patterns then try and figure out what’s behind them. For example, a Cupertino domain has been reading all of our automotive content very thoroughly. We also get hits by Google.com, Amazon.com, and dozens of other… Read More
Cadence loads up on MACs for vision with CNNs
For vision DSP IP running convolutional neural networks (CNNs), a big driver of performance is increasing the bits processed per cycle with parallel MACs. Tom Simon did a great job in recent posts of introducing CNNs at a high level, so I’ll look at what is architecturally behind Cadence’s latest announcement: the Tensilica Vision… Read More
Fast Track to a reconfigurable ASIC design
Licensing IP can be a pain, especially when the vendor’s business model has front-loaded costs to get started. Without an easy way to evaluate IP, justifying a purchase may be tough. With more mid-volume starts coming for the IoT, wearables, automotive, and other application segments, it’s a growing concern. Flex… Read More
Claude as an EDA Tool Wiki