Semiwiki 400x100 1 final
WP_Term Object
(
    [term_id] => 106
    [name] => FPGA
    [slug] => fpga
    [term_group] => 0
    [term_taxonomy_id] => 106
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 339
    [filter] => raw
    [cat_ID] => 106
    [category_count] => 339
    [category_description] => 
    [cat_name] => FPGA
    [category_nicename] => fpga
    [category_parent] => 0
    [is_post] => 
)
FPGA
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Partitioning for Prototypes

Partitioning for Prototypes
by Bernard Murphy on 09-19-2017 at 7:00 am
Categories: Aldec, EDA, FPGA, Prototyping

I earlier wrote a piece to make you aware of a webinar to be hosted by Aldec on some of their capabilities for partitioning large designs for prototyping. That webinar has now been broadcast and I have provided a link to the recorded version at the end of this piece. The webinar gets into the details of how exactly you would use the software… Read More

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Embedded FPGA IP as a Post-Silicon Debugger

Embedded FPGA IP as a Post-Silicon Debugger
by Tom Dillinger on 09-08-2017 at 12:00 pm
Categories: eFPGA, Flex Logix, FPGA, IP

The hardware functionality of a complex SoC is difficult to verify. Embedded software developed for a complex, multi-core SoC is extremely difficult to verify. An RTOS may need to be ported and validated. Application software needs to be developed, and optimized for performance. Sophisticated methodologies are employed to… Read More

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Webinar: Aiding ASIC Design Partitioning for multi-FPGA Prototyping

Webinar: Aiding ASIC Design Partitioning for multi-FPGA Prototyping
by Bernard Murphy on 09-07-2017 at 4:00 pm
Categories: Aldec, EDA, FPGA, Prototyping

The advantages of prototyping a hardware design on a FPGA platform are widely recognized, for software development, debug and regression in particular while the ultimate ASIC hardware is still in development. And if your design will fit into a single FPGA, this is not an especially challenging task (as long as you know your way … Read More

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Embedding FPGA IP

Embedding FPGA IP
by Bernard Murphy on 09-05-2017 at 7:00 am
Categories: Achronix, eFPGA, FPGA

The appeal of embedding an FPGA IP in an ASIC design is undeniable. For much of your design, you want all the advantages of ASIC: up to GHz performance, down to mW power (with active power management), all with very high levels of integration with a broad range of internal and 3[SUP]rd[/SUP]-party IP (analog/RF, sensor fusion, image/voice… Read More

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A Functional Safety Primer for FPGA – the White Paper

A Functional Safety Primer for FPGA – the White Paper
by Bernard Murphy on 08-23-2017 at 7:00 am
Categories: EDA, FPGA, Synopsys

Following up on their webinar on functional safety in FPGA-based designs, Synopsys have now published a white paper expanding on some of those topics. For those who didn’t get a chance to see the webinar this blog follows the white paper flow and is similar but not identical to my webinar blog, particularly around differences between… Read More

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Webinar: Fast-Track to Riviera-PRO

Webinar: Fast-Track to Riviera-PRO
by Bernard Murphy on 08-11-2017 at 7:00 am
Categories: Aldec, EDA, FPGA

Whether you’re right out of college, starting on your first design, a burn-and-churn designer thinking there must be a better way or an ASIC designer wanting to do a little prototyping, this webinar may be for you. It’s a fast start on using the Aldec Riviera-PRO platform for verification setup, run and debug, and more. There are … Read More

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FPGA-Based Networking for Datacenters: A Deeper Dive

FPGA-Based Networking for Datacenters: A Deeper Dive
by Bernard Murphy on 08-10-2017 at 7:00 am
Categories: Achronix, eFPGA, FPGA, Security

I’ve written before about the growing utility of FPGA-based solutions in datacenters, particularly around configurable networking applications. There I just touched on the general idea; Achronix have developed a white-paper to expand on the need in more detail and to explain how a range of possible solutions based on their … Read More

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Machine Learning Optimizes FPGA Timing

Machine Learning Optimizes FPGA Timing
by Bernard Murphy on 08-04-2017 at 7:00 am
Categories: AI, EDA, FPGA

Machine learning (ML) is the hot new technology of our time so EDA development teams are eagerly searching for new ways to optimize various facets of design using ML to distill wisdom from the mountains of data generated in previous designs. Pre-ML, we had little interest in historical data and would mostly look only at localized… Read More

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Cloud-Based Emulation

Cloud-Based Emulation
by Bernard Murphy on 08-02-2017 at 7:00 am
Categories: Aldec, EDA, FPGA
12 Comments

At the risk of attracting contempt from terminology purists, I think most of us would agree that emulation is a great way to prototype a hardware design before you commit to building, especially when you need to test system software together with that prototype. But setting up your own emulation resource isn’t for everyone. The … Read More

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A Functional Safety Primer for FPGA – and the Rest of Us

A Functional Safety Primer for FPGA – and the Rest of Us
by Bernard Murphy on 07-27-2017 at 7:00 am
Categories: Automotive, EDA, FPGA, Synopsys
6 Comments

Once in a while I come across a vendor-developed webinar which is so generally useful it deserves to be shared beyond the confines of sponsored sites. I don’t consider this spamming – if you choose you can ignore the vendor-specific part of the webinar and still derive significant value from the rest. In this instance, the topic is… Read More