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eFPGA
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Increased Processing Power Moves to Edge

Increased Processing Power Moves to Edge
by Tom Simon on 02-06-2018 at 12:00 pm
Categories: 5G, Achronix, Automotive, eFPGA, FPGA, IP

Recently there has been a lot of buzz about 5G networks. Aside from the talk about it possibly being nationalized, 5G will be a lot different than its predecessors. Rather than a single data link in a predetermined band, 5G will consist of a web of connections all working together to support existing types of data traffic and many new… Read More

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Adapting an embedded FPGA for Aerospace Applications

Adapting an embedded FPGA for Aerospace Applications
by Tom Dillinger on 01-30-2018 at 4:00 pm
Categories: eFPGA, Flex Logix, FPGA, IP

The IC industry is commonly divided into different market segments – consumer, mobile, industrial, commercial, medical, automotive, and aerospace. A key differentiation among these segments is the characterization and reliability qualification strategy for the fabrication process and design circuitry. For each segment,… Read More

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Moving from FPGA’s to Embedded FPGA Fabric – How it’s Done

Moving from FPGA’s to Embedded FPGA Fabric – How it’s Done
by Tom Simon on 01-15-2018 at 12:00 pm
Categories: Achronix, eFPGA, FPGA, IP

Buying IP is just a little bit more complicated than buying a pair of shoes. A lot of IP is configurable and requires attention to various design and configuration parameters. We live in an age where commercial soft IP is used pretty often in designs, so people have developed increasing comfort in the process that is required to achieve… Read More

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The lofty rise of the lowly FPGA

The lofty rise of the lowly FPGA
by Tom Simon on 01-10-2018 at 7:00 am
Categories: Achronix, eFPGA, FPGA, IP
4 Comments

FPGA programmable logic has served in many capacities since it was introduced back in the early 80’s. Recently, with designers looking for innovative ways to boost system performance, FPGA’s have moved front and center. This initiative has taken on new urgency with the slowing down of process node based performance gains. The… Read More

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"The Year of the eFPGA" 2017 Recap

"The Year of the eFPGA" 2017 Recap
by Tom Dillinger on 12-22-2017 at 7:00 am
Categories: eFPGA, Flex Logix, FPGA, IP

This past January, I had postulated that 2017 would be the “Year of the Embedded FPGA”, as a compelling IP offering for many SoC designs (link). As the year draws to a close, I thought it would be interesting to see how that prediction turned out.

The criteria that would be appropriate metrics include: increasing capital investment;… Read More

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DesignShare is all About Enabling Design Wins!

DesignShare is all About Enabling Design Wins!
by Daniel Nenni on 11-08-2017 at 7:00 am
Categories: eFPGA, Flex Logix, FPGA, IP, RISC-V, SiFive
5 Comments

One of the barriers to silicon success has always been design costs, especially if you are an emerging company or targeting an emerging market such as IoT. Today design start costs are dominated by IP which is paid at the start of the project and that is after costly IP evaluations and other IP verification and integration challenges.… Read More

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The perfect pairing of SOCs and embedded FPGA IP

The perfect pairing of SOCs and embedded FPGA IP
by Tom Simon on 10-30-2017 at 12:00 pm
Categories: Achronix, eFPGA, Events, FPGA, IP

In life, there are some things that just go together. Imagine the world without peanut butter and jelly, eggs and potatoes, telephones and voicemail, or the internet and search engines. In the world of computing there are many such examples – UARTS and FIFO’s, processor cores and GPU’s, etc. Another trait all these things have is… Read More

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Timing Analysis for Embedded FPGA’s

Timing Analysis for Embedded FPGA’s
by Tom Dillinger on 10-25-2017 at 7:00 am
Categories: eFPGA, Flex Logix, FPGA, IP
1 Comment

The initial project planning for an SoC design project faces a difficult engineering decision with regards to the “margin” that should be included as part of timing closure. For cell-based blocks, the delay calculation algorithms within the static timing analysis (STA) flow utilize various assumptions to replace… Read More

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How standard-cell based eFPGA IP can offer maximum safety, flexibility and TTM?

How standard-cell based eFPGA IP can offer maximum safety, flexibility and TTM?
by Eric Esteve on 10-19-2017 at 12:00 pm
Categories: eFPGA, FPGA, IP, Menta

Writing a white paper is never tedious, and when the product or the technology is emerging, it can become fascinating. Like for this white paper I have written for Menta “How Standard Cell Based eFPGA IP are Offering Maximum Flexibility to New System-on-Chip Generation”. eFPGA technology is not really emerging, but it’s fascinating… Read More

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How standard-cell based eFPGA IP can offer maximum safety, flexibility and TTM?

How standard-cell based eFPGA IP can offer maximum safety, flexibility and TTM?
by Eric Esteve on 10-19-2017 at 12:00 pm
Categories: eFPGA, FPGA, IP, Menta

Writing a white paper is never tedious, and when the product or the technology is emerging, it can become fascinating. Like for this white paper I have written for Menta “How Standard Cell Based eFPGA IP are Offering Maximum Flexibility to New System-on-Chip Generation”. eFPGA technology is not really emerging, but it’s fascinating… Read More