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Synopsys IP Designs Edge AI 800x100
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Timing Closure for ECOs in your SOC Design

Timing Closure for ECOs in your SOC Design
by Daniel Payne on 03-14-2012 at 1:07 pm

I decided to attend a webinar today hosted by Synopsys, “Streamline Your PrimeTime ECO Flow For Fastest Setup, Hold and Timing DRC Closure.” The format was to present slides first then hold for questions until the end. Enough time was spent on questions which made this webinar different than most other webinars I’ve… Read More


Common Platform Technology Forum: Peering into the Future

Common Platform Technology Forum: Peering into the Future
by Paul McLellan on 03-10-2012 at 9:00 am

Next Wednesday is the Common Platform Technology Forum. “Common Platform” is a name that only a committee could have come up with, giving no clue as to what it actually is. As you probably know, there are various process clubs sharing the costs of technology development (TD) and one of them consists of IBM, Samsung and… Read More


IC Custom IP Blocks – EM and IR Drop Effects

IC Custom IP Blocks – EM and IR Drop Effects
by Daniel Payne on 03-06-2012 at 5:33 pm

Designing custom IP blocks is a challenge at the transistor-level and I wanted to learn what the recommended methodology and EDA tool flow was at Synopsys. They have a webinar that you can register for and it takes 30 minutes to learn what they have to say, or you can read a White Paper. If you cannot spare that much time, then my summary… Read More


Test Synopsys offensive in VIP and try the quiz

Test Synopsys offensive in VIP and try the quiz
by Eric Esteve on 03-06-2012 at 11:33 am

I have recently blogged about Synopsys offensive in the Verification IP market. Did Synopsys again launched a new product, or announced a new acquisition? This would be a serious topic to blog, but today’s blog is closer to gaming than market analysis. Sometimes it’s good to have fun, even if the topic is serious! In fact, Synopsys… Read More


Designing ARM Powered High Performance SoCs on 28nm and 20nm!

Designing ARM Powered High Performance SoCs on 28nm and 20nm!
by Daniel Nenni on 03-06-2012 at 9:17 am


Last week I had an interesting meeting with GLOBALFOUNDRIES executives Kevin Meyer and Mojy Chian. It certainly seems that GFI has turned a corner! I will be in Dresden next week for DATE 2012 and will also visit the GFI Fab there. 28nm and 20nm are on track so expect an aggressive implementation plan from GFI this year.… Read More


HSPICE Users Talking about Their Circuit Simulation Experience

HSPICE Users Talking about Their Circuit Simulation Experience
by Daniel Payne on 02-28-2012 at 4:46 pm

tony todesco

HSPICE users gathered in January 2012 at the HSPICE SIG(Special Interest Group) to talk about their experiences using this circuit simulator for a variety of IC and signal integrity issues. I wasn’t able to attend in person however I did watch the video and wanted to summarize what I heard:… Read More


Synopsys at DVCon: tutorial, lunch, keynote, exhibits and more

Synopsys at DVCon: tutorial, lunch, keynote, exhibits and more
by Paul McLellan on 02-24-2012 at 1:10 pm

DVCon is next week, which I’m sure you know already if you are in verification. Of course Synopsys has a rich product portfolio in verification and verification IP (VIP) so is pretty visible at the show.

On Wednesday they are sponsoring lunch. Several Synopsys customers will talk about their view of how the verification landscape… Read More


Custom Processors: Webinar

Custom Processors: Webinar
by Paul McLellan on 02-21-2012 at 5:24 pm

What is a custom processor? Or Application Specific Instruction-set Processor (ASIP) which is the buzzword which may or may not catch on.

Most programming is done on a processor with a fixed instruction set: think Intel x86 or ARM. Intel or ARM decided on what instructions to include, based on a lot of benchmarking across a wide range… Read More


Multicore SoC Architecture Optimization

Multicore SoC Architecture Optimization
by Eric Esteve on 02-16-2012 at 5:36 am

Once again with Synopsys and Arteris, the innovation is coming to solve an issue, faced by their potential customers: “In our research, we’ve found that almost half of project delays are caused by problems with the system architecture design and specification,” said Chris Rommel, vice president, embedded… Read More