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Synopsys
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More to the story than bigger FPGA-based prototyping

More to the story than bigger FPGA-based prototyping
by Don Dingee on 08-19-2013 at 5:00 pm
Categories: EDA, FPGA, Synopsys

Still not convinced on the value of FPGA-based prototyping systems, or using older technology? I’ve been trying to find the story beyond just bigger, badder FPGAs in a box that you pour RTL into – and found some hints in a webinar on the Synopsys HAPS-70 from earlier this year.… Read More

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Why Adopt Hierarchical Test for SoC Designs

Why Adopt Hierarchical Test for SoC Designs
by Daniel Payne on 08-15-2013 at 4:37 pm
Categories: EDA, Synopsys, TSMC

IC designers have been creating with hierarchy for years to better manage large design sizes, however for the test world the concept of hierarchy and emerging standards is a bit newer. TSMC and Synopsys jointly created a webinarthat addresses hierarchical test, so I’ve attended it this week and summarized my findings here.… Read More

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♫ IMG Sitting on the DOK of the Bay…Closin’ Timin’

♫ IMG Sitting on the DOK of the Bay…Closin’ Timin’
by Paul McLellan on 07-24-2013 at 7:00 am
Categories: EDA, Imagination Technologies, IP, Synopsys

Scott Fitzgerald is supposed to have said “the rich are not like other people” to Ernest Hemingway (he didn’t). In the same way, processors are not like other blocks, and not because they have more gates (they don’t). However, special approaches to optimizing processors are important because the clock… Read More

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Debugging Verification Constraints

Debugging Verification Constraints
by Paul McLellan on 07-23-2013 at 3:44 pm
Categories: Arm, EDA, IP, Synopsys

In his DAC keynote last year (2012) Mike Mueller of ARM compared how much CPU was required to verify the first ARM versus one of the latest ARM Cortex CPUs. Of course the newer CPU is hundreds of times larger than the first ARM but the amount of verification required was millions of times as much, requiring ARM to construct their own datacenter… Read More

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The fixed and the finite: QoR in FPGAs

The fixed and the finite: QoR in FPGAs
by Don Dingee on 07-22-2013 at 1:00 pm
Categories: EDA, FPGA, Synopsys

There is an intriguingly amorphous term in FPGA design circles lately: Quality of Results, or QoR. Fitting a design in an FPGA is just the start – is a design optimal in real estate, throughput, power consumption, and IP reuse? Paradoxically, as FPGAs get bigger and take on bigger signal processing problems, QoR has become a larger… Read More

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Minimize the Cost of Testing ARM® Processor-based Designs and Other Multicore SoCs

Minimize the Cost of Testing ARM® Processor-based Designs and Other Multicore SoCs
by Daniel Payne on 07-15-2013 at 1:37 pm
Categories: EDA, FPGA, Synopsys

On my first job out of college as an IC design engineer I was surprised to discover that a major cost of chips was in the amount of time spent on the tester before being shipped. That is still true today, so how would you keep your tester time down, test coverage high and with a minimum number of pins when using multiple processors on a single… Read More

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Workload-tuned cores seeing greater interest

Workload-tuned cores seeing greater interest
by Don Dingee on 06-30-2013 at 10:00 pm
Categories: EDA, Synopsys

Is it possible to design a processor with very high performance and low power consumption? To answer that, embedded illuminati are now focusing on designs tuned to specific workloads – creating a tailored processor that does a few things very efficiently, with nothing extra.… Read More

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Aart: Technomic Push-Pull

Aart: Technomic Push-Pull
by Paul McLellan on 06-26-2013 at 11:00 pm
Categories: EDA, Synopsys

Aart de Geus gave one of the visionary look to the next 50 years of EDA as a warmup to Stephen Wu’s keynote. EDA is enabling the greatest push-pull ever, part of an exponential change on a scale never before seen.

Technologies seem to go through a 50 year technical push phase (driven by improving the technology) followed by a 50… Read More

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Fujitsu, Mediatek, Richtek and Synopsys om Custom IC Design

Fujitsu, Mediatek, Richtek and Synopsys om Custom IC Design
by Daniel Payne on 06-24-2013 at 3:01 pm
Categories: EDA, Synopsys

Synopsys has been acquiring EDA and IP companies at a fast clip over the past few years and it’s often made me wonder how they are going to craft a coherent tool flow for custom IC design. At DACthis year I learned that for schematic capture the winning tool is Custom Designer SE– a relatively new tool, while the IC layout… Read More

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Can we really find a way to speed-up Processor & DSP core designs?

Can we really find a way to speed-up Processor & DSP core designs?
by Eric Esteve on 06-21-2013 at 9:05 am
Categories: EDA, Imagination Technologies, IP, Synopsys

Once upon a time, ASIC designers involved in Processor design, like I was, for the first time in 1987 for Thomson CSF and again in 1994 for Texas Instruments, at that time supporting height (8) ASIC designed by another French company, the Advanced Computer Research Institute (ACRI), had to re-invent the wheel almost every day. When… Read More