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Synopsys AMD 5 21 25 Webinar 800x100 High Quality
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WEBINAR: Intel Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs

WEBINAR: Intel Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs
by Synopsys on 08-30-2022 at 10:00 am

Synopsys Fusion Compiler

Synopsys Fusion Compiler offers advanced optimizations to achieve the best PPA (power, performance, area) on today’s high-performance cores and interconnect designs. However, advanced transformation techniques available in synthesis such as retiming, multi-bit registers, advanced datapath optimizations, etc. are

Read More

An EDA AI Master Class by Synopsys CEO Aart de Geus

An EDA AI Master Class by Synopsys CEO Aart de Geus
by Daniel Nenni on 08-19-2022 at 8:00 am

Aart de Geus White House

I consider Dr. Aart de Geus one of the founding fathers of EDA and one of the most interesting people in the semiconductor industry. So it is not a surprise that Aart was chosen to attend the CHIPs Act signing at the White House.

Here is his current corporate bio:

Since co-founding Synopsys in 1986, Dr. Aart de Geus has expanded Synopsys… Read More


WEBINAR: Design and Verify State-of-the-Art RFICs using Synopsys / Ansys Custom Design Flow

WEBINAR: Design and Verify State-of-the-Art RFICs using Synopsys / Ansys Custom Design Flow
by Synopsys on 08-11-2022 at 8:00 am

Synopsys Ansys RF Flow Webinar

The design and characterization of RF circuits is a complex process that requires an RF designer to overcome a variety of challenges. Not only do they face the complexities posed by advanced semiconductor processes and the need to meet the demanding requirements of modern wireless standards, designers must also account for electromagnetic… Read More


DSP IP for High Performance Sensor Fusion on an Embedded Budget

DSP IP for High Performance Sensor Fusion on an Embedded Budget
by Kalar Rajendiran on 08-04-2022 at 6:00 am

VPX Vector DSP Core Data Types

Whether we realize it or not, everyday applications we use depend on data gathered by sensors. We can bet that pretty much every application uses at least a couple of different types of sensors, if not more. That is because different types of sensors are better suited to collect data depending on the application, the environment … Read More


Intelligently Optimizing Constrained Random

Intelligently Optimizing Constrained Random
by Bernard Murphy on 07-12-2022 at 6:00 am

Potential coverage problems min

“Who guards the guardians?” This is a question from Roman times which occurred to me as relevant to this topic. We use constrained random to get better coverage in simulation. But what ensures that our constrained random testbenches are not wanting, maybe over constrained or deficient in other ways? If we are improving with a faulty… Read More


Using STA with Aging Analysis for Robust IC Designs

Using STA with Aging Analysis for Robust IC Designs
by Daniel Payne on 06-23-2022 at 10:00 am

Gate Level Aging min

Our laptops and desktop computers have billions of transistors in their application processor chips, yet I often don’t consider the reliability effects of aging that the transistors experience in the chips. At the recent Synopsys User Group (aka SNUG), there was a technical presentation on this topic from Srinivas Bodapati,… Read More


Casting Light on OpenLight’s Open Silicon Photonics Platform

Casting Light on OpenLight’s Open Silicon Photonics Platform
by Kalar Rajendiran on 06-20-2022 at 6:00 am

The Growing Silicon Photonics Market

For many decades now, modern optical technology has been deployed in networking infrastructure, for long haul and medium haul links to support internet communications. The foundation of this technology is photonics, which is the science of generation, manipulation and detection of light for performing functions otherwise… Read More


DesignDash: ML-Driven Big Data Analytics Technology for Smarter SoC Design

DesignDash: ML-Driven Big Data Analytics Technology for Smarter SoC Design
by Kalar Rajendiran on 06-06-2022 at 10:00 am

DesignDash Better Decisions Faster

With time-to-market pressures ever increasing, companies are continually seeking enhanced designer productivity, faster design closure and improved project management efficiency. To accomplish these, organizations invest a lot in implementing both standardized approaches and proprietary techniques. With ever increasing… Read More


Coding Guidelines for Datapath Verification

Coding Guidelines for Datapath Verification
by Bernard Murphy on 06-01-2022 at 6:00 am

multiplier min

It has been an article of faith that you can’t use formal tools to validate datapath logic (math components). Formal is for control logic, not datapath, we now realize. We understood the reason – wide inputs (32-bit, 64-bit or more) fed through a multiplier deliver eye-watering state space sizes. State space explosions also happen… Read More


Very Short Reach (VSR) Connectivity for Optical Modules

Very Short Reach (VSR) Connectivity for Optical Modules
by Kalar Rajendiran on 05-26-2022 at 6:00 am

Synopsys 112G Ethernet PHY IP for VSR

Bandwidth, latency, power and reach are always the key points of focus when it comes to connectivity. As the demand for more data and higher bandwidth connectivity continue, power management is gaining a lot of attention. There is renewed interest in pursuing silicon photonics to address many of these challenges. There are many… Read More