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Silvaco on Simulation of Reliability and NBTI Aging in MOS Microelectronics

Silvaco on Simulation of Reliability and NBTI Aging in MOS Microelectronics
by Daniel Nenni on 02-20-2019 at 12:00 pm

Silvaco was founded the same year I entered the EDA industry (1984) fresh from University. I first met them at the Design Automation Conference in Albuquerque, New Mexico, and have been an active observer of their growth ever since. In fact, Silvaco is now the largest privately held EDA company and is growing at a rapid pace. In 2014… Read More


Where Circuit Simulation Model Files Come From

Where Circuit Simulation Model Files Come From
by Daniel Payne on 02-07-2019 at 7:00 am

I started out my engineering career by doing transistor-level circuit design and we used a proprietary SPICE circuit simulator. One thing that I quickly realized was that the accuracy of my circuit simulations depended entirely on the model files and parasitics. Here we are 40 years later and the accuracy of SPICE circuit simulations… Read More


The Latest in Parasitic Netlist Reduction and Visualization

The Latest in Parasitic Netlist Reduction and Visualization
by Tom Dillinger on 10-22-2018 at 12:00 pm

The user group events held by EDA companies offer a unique opportunity to hear from designers and CAD engineers who are actually using the EDA tools “in the trenches”. Some user presentations are pretty straightforward – e.g., providing a quality-of-results (QoR) design comparison when invoking a new tool feature added to a recent… Read More


Advanced Materials and New Architectures for AI Applications

Advanced Materials and New Architectures for AI Applications
by Tom Dillinger on 10-17-2018 at 7:00 am

Over the past 50 years in our industry, there have been three invariant principles:

  • Moore’s Law drives the pace of Si technology scaling
  • system memory utilizes MOS devices (for SRAM and DRAM)
  • computation relies upon the “von Neumann” architecture
Read More

Technology Behind the Chip

Technology Behind the Chip
by Daniel Nenni on 10-15-2018 at 7:00 am

Tom Dillinger and I attended the Silvaco SURGE 2018 event in Silicon Valley last week with several hundred of our semiconductor brethren. Tom has a couple blogs ready to go but first let’s talk about the keynote by Silvaco CEO David Dutton. David isn’t your average EDA CEO, he spent the first 8 years of his career at Intel then spent … Read More


SURGE 2018 Silvaco Update!

SURGE 2018 Silvaco Update!
by Daniel Nenni on 10-01-2018 at 7:00 am

The semiconductor industry has been very good to me over the past 35 years. I have had a front row seat to some of the most innovative and disruptive things like the fabless transformation and of course the Electronic Design Automation phenomenon, not to mention the end products that we as an industry have enabled. It is truly amazing… Read More


When it Comes to Process Migration, “Standard Cells” are Anything But

When it Comes to Process Migration, “Standard Cells” are Anything But
by Tom Simon on 08-22-2018 at 12:00 pm

Standard cell library developers are faced with a daunting task when it is time to create a library for a new process node. Porting an existing library can be a big help, but even then, manual modifications to 800 or more cells is still required. Each of those cells has many geometric elements are that affected by new design rules. All… Read More


SPICE Model Generation by Machine Learning

SPICE Model Generation by Machine Learning
by Thomas Blaesi on 05-18-2018 at 12:00 pm

It was 1988 when I got into SPICE (Simulation Program with Integrated Circuit Emphasis)while I was characterizing a 1.5 μm Standard cell library developed by students at my Alma-Mata Furtwangen University in Germany. My professor Dr. Nielinger was not only my advisor he also wrote the first SPICE bible in German language.… Read More


Sometimes a Solver is a Suitable Solution

Sometimes a Solver is a Suitable Solution
by Tom Simon on 04-17-2018 at 7:00 am

Traditional, rule based, RC extractors rely on a substantial base of assumptions, which are increasingly proving unreliable. Having accurate RC extraction results for parasitic R’s and C’s is extremely important for ensuring proper circuit operation and for optimizing performance and power. Advanced process nodes are making… Read More


Free Webinar: Silvaco 3D Solver Based Extraction for Device and Circuit Designers

Free Webinar: Silvaco 3D Solver Based Extraction for Device and Circuit Designers
by Tom Simon on 03-20-2018 at 12:00 pm

Designers spend a lot of time looking at their layouts in 2D. This is done naturally because viewing in 2D is faster and simpler than in 3D. It helps that humans are good at extrapolating from 2D to 3D. Analysis software, such as extraction software also spend a lot of time looking at layouts in 2D. While this is fine for approximate results,… Read More