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Webinar: OCV and Timing Closure Sign-off by Silvaco on Oct 10 at 10AM

Webinar: OCV and Timing Closure Sign-off by Silvaco on Oct 10 at 10AM
by Daniel Nenni on 10-01-2019 at 10:00 am

The old adage that goes the one constant thing you can always count on is change, could easily be reworded for semiconductor design to say the one constant thing you can count on is variation. This is doubly true. Not only is variation, in all its forms, a constant factor in design, additionally the methods of analyzing and dealing with are continuously changing as well. For both of these reasons it is necessary to stay current and on top of the latest developments in the role of variation in timing closure.

Designers are often faced with a tradeoff between less pessimistic results and extraordinarily long runtimes and large data sets. There is a long history of innovation that has brought us to what are considered the best approaches for massive designs. The foundation of the entire process relies on library characterization to produce models that support effective chip level analysis. Advanced nodes have further complicated the process.

Fortunately, Silvaco is offering a free webinar that will provide a useful update on both the history and state of the art for how on-chip variation can affect the sign-off timing flow. Silvaco has longstanding expertise at the process and cell level, as well as flows for chip level timing verification.

The October 10th webinar will be presented by Bernardo Culau, Director of Library Characterization at Silvaco. He has in-depth experience developing tools for library characterization. The topics that will be covered include:

    • What variation means in the context of library characterization
    • What on-chip variation is and its different causes
      • Inter-chip variation
      • Intra-chip variation
    • Review of different industry approaches to account for on-chip variation
      • OCV, AOCV, LVF
      • Their advantages and limitations
    • Current industry standards for variation-aware libraries
    • The improvements needed to handle leading-edge technology nodes
    • The characterization challenges involved in creating variation-aware libraries
    • Silvaco solutions for variation-aware library characterization

The free webinar will be offered at 10AM on October 10th. This seems like a good opportunity to stay current with the latest trends in a critical area of chip design. It also looks like it might provide a glimpse of what is ahead in this area. Should be interesting.

About Silvaco, Inc.
Silvaco Inc. is a leading EDA tools and semiconductor IP provider used for process and device development for advanced semiconductors, power IC, display and memory design. For over 30 years, Silvaco has enabled its customers to develop next generation semiconductor products in the shortest time with reduced cost. We are a technology company outpacing the EDA industry by delivering innovative smart silicon solutions to meet the world’s ever-growing demand for mobile intelligent computing. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia.