Flash memory has become ubiquitous, so much so that it is easy to forget what life before it was like. Large scale non-volatile storage was limited spinning disks, which were bulky, power hungry and unreliable. With NAND Flash, we have become used to carrying many gigabytes around with us all the time in the form of cell phones, USB drives, camera SD cards, even laptops. NAND Flash has been a key enabler for dozens of devices that we use on a daily basis. Because they work so well, they have become taken for granted. In one respect this is a good thing, the best technology is that which blends into our lives and does not stand out glaringly.
Yet, the design of 3D NAND devices is complex and requires a great deal of care and consideration. Designers of 3D NAND memories struggle to balance competing requirements in the design of the memory cells. One area that is particularly interesting is the design of the select gate transistor. When optimized properly it is able to drive the bit in question but will not affect adjacent bits.
Silvaco is planning a webinar on November 21st at 10AM PST that will cover the challenges found in designing optimized 3D NAND. Silvaco will present the usage of TCAD process and device software for optimizing the operation of a 3D NAND memory cell with a focus on the select gate transistor. The end result will be a simulation of the 3D NAND cell operation that includes read/program, erase and program disturb error.
The presenter will be Dr Jin Cho, Principal Application Engineer at Silvaco. Prior to joining Silvaco he has over 15 years of experience in process/device management, including 14/10nm logic technology development. He also has managed a TCAD group for future device development technology. He holds a PhD. From Stanford University.
This technically oriented webinar will thoroughly explore the specifics of 3D NAND design and should be extremely informative. Registration and more details about the webinar are available on the Silvaco website.