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Q2FY24TessentAI 800X100
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Addressing Moore’s Law with the First Law of Real Estate: Location, location, location

Addressing Moore’s Law with the First Law of Real Estate: Location, location, location
by Beth Martin on 08-02-2015 at 7:00 am

Design sizes and complexities have grown exponentially (it’s a Law!), and consequentially the task of silicon test has become proportionally more expensive. The cost of testing a device is proportional to the amount of test data that is applied, and therefore the time it takes, which in turn is proportional to both design size … Read More


Boost the Market for Interposer and 3D ICs with Assembly Design Kits

Boost the Market for Interposer and 3D ICs with Assembly Design Kits
by Beth Martin on 07-29-2015 at 6:00 pm

The traditional system-on-chip (SoC) design process has fully qualified verification methods embodied in the form of process design kits (PDKs). Why is it that chip design companies and assembly houses have no IC/package co-design sign-off verification process?

Package die are often produced using multiple processes and… Read More


Power Analysis Needs Shift in Methodology

Power Analysis Needs Shift in Methodology
by Pawan Fangaria on 07-26-2015 at 7:00 am

It’s been the case most of the time that until we hit a bottleneck situation, we do not realize that our focus is not at the right spot. Similar is the case with power analysis at the SoC level. Power has become equally if not more important than the functionality and other parameters of an SoC, and therefore has to be verified earlier … Read More


Device Noise Analysis, What Not to Do for AMS IC Designs

Device Noise Analysis, What Not to Do for AMS IC Designs
by Daniel Payne on 07-24-2015 at 12:00 pm

AMS IC designers have a lot to think about when crafting transistor-level designs to meet specifications and schedules, so the most-used tool in their kit is the trusted SPICE or FastSPICE circuit simulator to help analyze timing, power, sensitivity and even device noise. I just did a Google search for “device noise analysisRead More


How PowerArtist Interfaces with Emulators

How PowerArtist Interfaces with Emulators
by Pawan Fangaria on 07-16-2015 at 5:00 pm

Last month in DAC I could see some of the top innovations in the EDA world. EDA is a key enabler for advances in semiconductor designs. Among a number of innovations worth mentioning (about which I blogged just after DAC), the integration of Mentor’s Veloce with ANSYS’ PowerArtist for power analysis of live applications caught my… Read More


Power Management Gets Tricky in IP Driven World

Power Management Gets Tricky in IP Driven World
by Pawan Fangaria on 07-08-2015 at 7:00 pm

Today, an SoC can have multiple instances of an IP and also instances of many different IPs from different vendors. Every instance of an IP can work in a separate mode and requires a dedicated power arrangement which may only be formalized at the implementation stage. The power intent, if specified earlier, will need to be re-generated… Read More


What’s New in Functional Verification Debug

What’s New in Functional Verification Debug
by Daniel Payne on 06-28-2015 at 7:00 am

We often think of EDA vendors competing with each other and using proprietary data formats to make it difficult for users to mix and match tools, or even create efficient flows of tools. At the recent DAC event in San Francisco I was pleasantly surprised to hear that two EDA vendors decided to cooperate instead of create incompatible… Read More


Predicting Lifetime of Analog ICs

Predicting Lifetime of Analog ICs
by Pawan Fangaria on 06-22-2015 at 12:30 pm

With the increase of transistors per unit area, high density interconnects and manufacturing variability at lower nodes, the electronic devices have become more vulnerable to failures. The devices that operate under extreme conditions such as automotive devices that operate at high temperatures need to be robust enough to… Read More


The Best Conversations You Missed at #52DAC!

The Best Conversations You Missed at #52DAC!
by Daniel Nenni on 06-17-2015 at 7:00 pm

The CEO Fireside Chats were my very favorite part of #52DAC. Dr. Walden Rhines, Lip-Bu Tan, and Dr. Aart de Geus are heroes of the EDA industry, absolutely. I saw all three Fireside Chats and the one word that I’m left with is INSPIRED! … Read More


Why silicon photonics and 2.5D design go together

Why silicon photonics and 2.5D design go together
by Beth Martin on 06-10-2015 at 4:30 pm

Silicon photonics is one of the upstart “More than Moore” technologies designed to enable the next generation of high-performance devices. Photonic design is the art of moving and transforming signals in the form of photons, allowing the message to literally travel at the speed of light, and bringing the promise of significant… Read More