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Electronic Design Automation
About once a quarter, I touch base with Cristian Amitroaie, CEO and co-founder of AMIQ EDA, to see what’s new with the company, products, and users. Sometimes he surprises me, as he did earlier this year when he mentioned that their tools check about 150 rules for non-standard constructs in SystemVerilog and VHDL. When we talked … Read More
Leveraging neural nets and CR testing isn’t as simple as we first thought. But is that the last word in combining these two techniques? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and I continue our series on research ideas. As always, feedback welcome.… Read More
Glitches on clock domain crossing signals have always been a concern for chip designers. Now with increased requirements for reliability, renewed scrutiny is being given to find ways to identify these problems and fix them. In particular applications such as automotive electronics have given this added effort an impetus. Siemens… Read More
Cadence hosted its annual CadenceLIVE Americas conference June 8th-June 9th. Four keynotes and eighty-three different talks on various topics were presented. The talks were delivered by Cadence, its customers and partners.
The C-suite keynotes were delivered by Lip-Bu Tan (CEO) and Dr. Anirudh Devgan (President). The talks… Read More
One of the most unique acronyms that I learned about this past year is ACAP from Xilinx, which stands for Adaptive Compute Acceleration Platform. At the recent Cadence LIVE event, I had the pleasure of watching Pei Yao, a Xilinx senior staff CAD engineer, as she talked about the challenges of getting all the analog and mixed-signals… Read More
Last week, Cadence hosted its annual CadenceLIVE Americas conference. Four keynotes and eighty-three different talks on various topics were presented. The talks were delivered by Cadence, its customers and partners.
This blog is about the two keynotes delivered by CEO Lip-Bu Tan and President Dr. Anirudh Devgan. The guest … Read More
This summer, I got the opportunity to work as a Formal Verification Intern with Axiomise for six weeks. I’m a keen designer and love working in design and architecture. Although, I’ve not started my professional career yet, I have done most of my projects as a designer in my undergraduate and postgraduate studies.
Having said that,… Read More
I first remember blogging about EDA in the cloud starting back in 2011, so what’s changed in the last 10 years you may ask? In 2011, it was basically a handful of EDA point tools running batch mode in the cloud, and you were on your own to integrate those into a coherent flow, so expect help from the CAD and IT departments for sure.… Read More
If you ascribe to the notion that things move in circles, or concentrically, the move to die-to-die connectivity makes complete sense. Just as multi-chip modules (MCM) were the right technology decades ago to improve power, areas, performance and cost, the use of chiplets with die-to-die connections provides many advantages… Read More
I would contend there is no job quite like working as a support engineer for a simulation tool like Ansys HFSS. Such a role forces an engineer to understand technology in breadth and depth like no other because HFSS is applied to such a broad range of applications and products throughout the world. My own introduction to HFSS began … Read More
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