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New Mixed-Signal Simulation Features from Siemens EDA at DAC

New Mixed-Signal Simulation Features from Siemens EDA at DAC
by Daniel Payne on 07-13-2022 at 10:00 am

Symphony Pro for mixed-signal verification

It’s the second day of DAC, and the announcements are coming in at a fast pace, so stay tuned to SemiWiki for all of the latest details. As a long-time SPICE user and industry follower, I’ve witnessed the progression as EDA vendors have connected their SPICE simulators to digital simulators, opening up a bigger world… Read More


What’s New With Calibre at DAC This Year?

What’s New With Calibre at DAC This Year?
by Daniel Payne on 07-12-2022 at 9:00 am

whats changed min

When I worked at EDA vendors and attended DAC, one of the most popular questions asked in the booth and suites was simply, “What’s new this year?” It’s a fair question, and yet many semiconductor professionals are so focused on their present project, using their familiar methodology, that they simply… Read More


Intelligently Optimizing Constrained Random

Intelligently Optimizing Constrained Random
by Bernard Murphy on 07-12-2022 at 6:00 am

Potential coverage problems min

“Who guards the guardians?” This is a question from Roman times which occurred to me as relevant to this topic. We use constrained random to get better coverage in simulation. But what ensures that our constrained random testbenches are not wanting, maybe over constrained or deficient in other ways? If we are improving with a faulty… Read More


Memory Security Relies on Ultra High-Performance AES-XTS Encryption/Decryption

Memory Security Relies on Ultra High-Performance AES-XTS Encryption/Decryption
by Kalar Rajendiran on 07-11-2022 at 10:00 am

dwtb q222 security aes xts fig1.jpg.imgw .850.x

A recent SemiWiki post covered the topic of protecting high-speed interfaces in data centers using security IP. That post was based on a presentation made by Dana Neustadter at IP-Soc Silicon Valley 2022 conference. Dana’s talk was an overview of various interfaces and Synopsys’ security IP for protecting those interfaces. … Read More


Can We Auto-Generate Complete RTL, SVA, UVM Testbench, C/C++ Driver Code, and Documentation for Entire IP Blocks?

Can We Auto-Generate Complete RTL, SVA, UVM Testbench, C/C++ Driver Code, and Documentation for Entire IP Blocks?
by Kalar Rajendiran on 07-11-2022 at 6:00 am

IDSNG1

Whether it is fully autonomous driving, or wrinkle-free fabric, or ambient energy harvesting for powering electronic devices, each industry is chasing after its respective ultimate goal. For the semiconductor design industry, its goal is the capability to generate complete chip or IP in executable format from a high-level… Read More


Altair at #59DAC with the Concept Engineering Acquisition

Altair at #59DAC with the Concept Engineering Acquisition
by Daniel Nenni on 07-07-2022 at 10:00 am

Altair HPC Banner

The Design Automation Conference has been the pinnacle for semiconductor design for almost 60 years. This year will be my 38th DAC and I can’t wait to see everyone again. One of the companies I will be spending time with this year is Altair.

Last month Altair acquired our friends at Concept Engineering, the leading provider… Read More


CXL Verification. A Siemens EDA Perspective

CXL Verification. A Siemens EDA Perspective
by Bernard Murphy on 07-07-2022 at 6:00 am

CXL Verification

Amid the alphabet soup of inter-die/chip coherent access protocols, CXL is gaining a lot of traction. Originally proposed by Intel for cross-board and cross-backplane connectivity to accelerators of various types (GPU, AI, warm storage, etc.), a who’s who of systems and chip companies now sits on the board, joined by an equally… Read More


What Quantum Means for Electronic Design Automation

What Quantum Means for Electronic Design Automation
by Kelly Damalou and Kostas Nikellis on 07-06-2022 at 10:00 am

Ansys quantum blog Image1

In 1982, Richard Feynman, a theoretical physicist and Nobel Prize winner, proposed the initial quantum computer; Feynman’s quantum computer would have the capacity to facilitate traditional algorithms and quantum circuits with the goal of simulating quantum behavior as it would have occurred in nature. The systems Feynman… Read More


Multi-FPGA Prototyping Software – Never Enough of a Good Thing

Multi-FPGA Prototyping Software – Never Enough of a Good Thing
by Daniel Nenni on 07-06-2022 at 8:00 am

PlayerPro EN

Building a multi-FPGA prototype for SoC verification is complex with many interdependent parts – and is “always on a clock”.  The best multi-FPGA prototype implementation is worthless if its not up and running early in the SoC design cycle, where it offers the highest verification ROI terms of minimizing the cost of bug fixes … Read More


Jade Design Automation’s Register Management Tool

Jade Design Automation’s Register Management Tool
by Kalar Rajendiran on 07-05-2022 at 10:00 am

RegMan supervisor CSRs

When more than one person is working on any project, coordination is imperative. When the team size grows, being in sync becomes essential. When it comes to SoC design management, registers and bit fields are used to communicate status of results and execute conditional controls. The Register Management function plays an essential… Read More