Events EDA2025 esig 2024 800X100
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A Closer Look at Conquering Clock Jitter with Infinisim

A Closer Look at Conquering Clock Jitter with Infinisim
by Mike Gianfagna on 08-26-2024 at 6:00 am

A Closer Look at Conquering Clock Jitter with Infinisim

As voltages go down and frequencies increase, the challenges in chip design become increasingly complex and unforgiving. Issues that once seemed manageable now escalate, while new obstacles emerge, demanding our attention. Among these challenges, clock jitter stands out as a formidable threat. At its core, clock jitter is… Read More


Overcoming Verification Challenges of SPI NAND Flash Octal DDR

Overcoming Verification Challenges of SPI NAND Flash Octal DDR
by Kalar Rajendiran on 08-22-2024 at 10:00 am

Typical Octal Serial NAND Device

As the automotive industry continues to evolve, the demands for high-capacity, high-speed storage solutions are intensifying. Autonomous vehicles and V2X (Vehicle-to-Everything) communication systems generate and process massive amounts of data, necessitating advanced storage technologies capable of meeting these… Read More


Introducing XSim: Achieving high-quality Photonic IC tape-outs

Introducing XSim: Achieving high-quality Photonic IC tape-outs
by jrobcary on 08-21-2024 at 10:00 am

txcorp XSim Example Photonics

Similar to analog circuits, which use EM waves at communications frequencies, components in photonics integrated circuits (PICs), which use EM waves at optical frequencies, are sensitive to layout and manufacturing variations—arguably more so.  Similar to their semiconductor counterparts, which transmit information… Read More


Synopsys IP Processor Summit 2024

Synopsys IP Processor Summit 2024
by Daniel Nenni on 08-21-2024 at 6:00 am

Synopsys Processor Summit

Now that live events are filling up there are even more live events especially here in Silicon Valley. Synopsys, the #1 full IP provider, will host a processor summit here in Santa Clara next month. Given the popularity of anything RISC-V, I would expect this event to be very well attended so be sure and register in advance.

The networking… Read More


What are Cloud Flight Plans? Cost-effective use of cloud resources for leading-edge semiconductor design

What are Cloud Flight Plans? Cost-effective use of cloud resources for leading-edge semiconductor design
by Christopher Clee on 08-19-2024 at 10:00 am

fig1 vpc

Embracing cloud computing is highly attractive for users of electronic design automation (EDA) tools and flows because of the productivity gains and time to market advantages that it can offer. For Siemens EDA customers engaged in designing large, cutting-edge chips at advanced nanometer scales, running Calibre® design stage… Read More


The Impact of UCIe on Chiplet Design: Lowering Barriers and Driving Innovation

The Impact of UCIe on Chiplet Design: Lowering Barriers and Driving Innovation
by Kalar Rajendiran on 08-15-2024 at 6:00 am

Comparative Analysis of Chiplet Interconnect Standards (Physical Layer)

The semiconductor industry is experiencing a significant transformation with the advent of chiplet design, a modular approach that breaks down complex chips into smaller, functional blocks called chiplets. A chiplet-based design approach offers numerous advantages, such as improved performance, reduced development … Read More


First third-party ISO/SAE 21434-certified IP product for automotive cybersecurity

First third-party ISO/SAE 21434-certified IP product for automotive cybersecurity
by Don Dingee on 08-14-2024 at 6:00 am

ISO/SAE 21434 and UNECE WP.29 R155

Increased processing and connectivity in automobiles are cranking up the priority for advanced cybersecurity steps to keep roads safe. Electronic vehicle interfaces, including 5G/6G, Bluetooth, Wi-Fi, GPS, USB, CAN, and others, offer convenience features for drivers and passengers, but open numerous attack vectors for… Read More


Circuit Simulation Update from Empyrean at #61DAC

Circuit Simulation Update from Empyrean at #61DAC
by Daniel Payne on 08-13-2024 at 10:00 am

Empyrean SPICE min

A familiar face in EDA, Greg Lebsack met with me in the Empyrean booth at DAC this year on opening day to provide an update on what’s new. I first met Greg when he was at Tanner EDA, then Mentor and Siemens EDA, so he really knows our industry quite well. The company was a Silver level sponsor of DAC this year, and Empyrean offers tools for… Read More


The Future of Logic Equivalence Checking

The Future of Logic Equivalence Checking
by Bernard Murphy on 08-07-2024 at 6:00 am

LEC concept

Logic equivalence checking (LEC) is an automated process to verify that modified versions of a design evolving through implementation remain logically equivalent to the functionally signed-off RTL. This becomes important when accounting for retiming optimizations and for necessary implementation-stage ECOs which must… Read More


Aniah and Electrical Rule Checking (ERC) #61DAC

Aniah and Electrical Rule Checking (ERC) #61DAC
by Daniel Payne on 08-06-2024 at 10:00 am

Aniah #61DAC min

Visiting a new EDA vendor at #61DAC is always a treat, because much innovation comes from the start-up companies, instead of the established big four EDA companies. I met with Vincent Bligny, Founder and CEO of Aniah on Wednesday in their booth, to hear about what they are doing differently in EDA. Mr. Bligny has a background working… Read More